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| m pd17134a m pd17135a m pd17136a m pd17137a m pd17p136a m pd17p137a 1993 m pd17134a subseries 4-bit single-chip microcontroller document no. u11607ej3v0um00 (3rd edition) date published december 1996 n printed in japan
notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8 the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 the export of this product from japan is prohibited without governmental license. to export or re-export this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. simplehost is a trademark of nec corp. ms-dos and windows are trademarks of microsoft corp. pc/at and pc dos are trademarks of ibm corp. major revisions in this edition page description throughout change of name m pd1713xa to m pd17134a subseries p. 5 correction of (2) program memory write/verify mode in 1.4 pin configuration p. 18 change of figure 3-2 value of program counter after instruction partial correction of 3.2.2 on execution of branch instruction (br) p. 19 partial correction of 3.2.3 on during execution of subroutine call p. 23 change of chapter 4 program memory (rom) p. 31 partial correction of figure 5-1 data memory configuration p. 35 change of chapter 6 stack p. 43 partial correction of 7.2.2 address register functions p. 47 change of 7.5 index register (ix) and data memory row address pointer (memory pointer: mp) p. 58 partial change of 7.6.2 functions of general register pointer p. 59 partial change of 7.7.1 program status word configuration p. 61 change of 7.7.4 zero flag (z) and compare flag (cmp) p. 61 partial correction of 7.7.5 carry flag (cy) p. 71 partial correction of 9.2.3 register file manipulation instructions p. 111 change of chapter 13 peripheral hardware p. 149 change of chapter 14 interrupt functions p. 169 change of chapter 16 standby function p. 179 change of chapter 17 reset p. 190 partial change of table 18-2 differences between mask rom version and one- time prom version p. 194 partial change of 19.3 list of the instruction set p. 198 partial change of 19.5 instructions p. 255 change of chapter 20 assembler reserved words p. 257 partial change of 20.2 reserved symbols p. 261 addition of appendix a development of m pd171 subseries p. 263 addition of appendix b comparison of functions between m pd17135a, 17137a, and m pd17145 subseries p. 267 addition of appendix d notes on configuration of system clock oscillation circuit the mark shows major revisions made in this edition. preface target : this manual is intended for user engineers who understand the functions of each product in the m pd17134a subseries and try to design application systems using the m pd17134a subseries. purpose : the purpose of this manual is for the user to understand the hardware functions of the m pd17134a subseries. use : the manual assumes that the reader has a general knowledge of electricity, logic circuits, microcomputers. ? to understand the functions of the m pd17134a subseries in a general way; ? read the manual from contents . ? to look up instruction functions in detail when you know the mnemonic of an instruction; ? use appendix e instruction list . ? to look up an instruction when you do not know its mnemonic but know outlines of the function; ? refer to 19.3 list of the instruction set for search for the mnemonic of the instruction, then see 19.5 instructions for the functions. ? to learn the electrical specifications of the m pd17134a subseries ? refer to the data sheet available separately. ? to learn the application examples of the functions of the m pd17134a subseries ? refer to the application note available separately. legend : data representation weight : high-order and low-order digits are indicated from left to right. active low representation : (pin or signal name is overlined) memory map address : top: low-order, bottom: high-order note : explanation of note in the text caution : caution to which you should pay attention remark : supplementary explanation to the text number representation : binary number ... or b decimal number ... hexadecimal number ... h related documents : the following documents are provided for the m pd17134a subseries. the numbers listed in the table are the document numbers. product name m pd17134a m pd17135a m pd17136a m pd17137a m pd17p136a m pd17p137a document name brochure if-1166 if-1169 if-1166 if-1169 if-1168 if-1165 data sheet u10591e u10592e u10591e u10592e ic-2871 ic-2872 users manual ieu-1369 application note iea-1297 (introduction), iea-1293 (rice cooker, thermos bottle) ie-17k (ver. 1.6) eeu-1467 users manual ie-17k-et (ver. 1.6) eeu-1466 users manual se board eeu-1379 users manual simplehost tm eeu-1336 (introduction), eeu-1337 (reference) users manual as17k assembler eeu-1287 users manual device file u10777e users manual pin name and symbol name should be read according to the system clock type. system clock rc oscillation ceramic oscillation m pd17134a m pd17135a m pd17136a m pd17137a pin name, symbol name m pd17p136a m pd17p137a pin for system clock oscillation osc 1 x in osc 0 x out system clock f cc f x - i - table of contents chapter 1 general description ................................................................................................. 1 1.1 function list ............................................................................................................................... ......... 2 1.2 ordering information ..................................................................................................................... 3 1.3 block diagram ............................................................................................................................... ..... 4 1.4 pin configuration (top view) ........................................................................................................ 5 chapter 2 pin functions ............................................................................................................... 9 2.1 pin functions ............................................................................................................................... ........ 9 2.2 pin input/output circuit ............................................................................................................... 11 2.3 processing of unused pins ......................................................................................................... 14 2.4 notes on using reset pin and p1b 0 pin ................................................................................... 15 chapter 3 program counter (pc) ........................................................................................... 17 3.1 program counter configuration ............................................................................................ 17 3.2 program counter operation ..................................................................................................... 17 3.2.1 at reset ............................................................................................................................... ...... 18 3.2.2 during execution of the branch instruction (br) ..................................................................... 18 3.2.3 during execution of subroutine calls (call) .......................................................................... 19 3.2.4 during execution of return instructions (ret, retsk, reti) ............................................... 20 3.2.5 during table reference (movt) .............................................................................................. 20 3.2.6 during execution of skip instructions (ske, skge, sklt, skne, skt, skf) ...................... 21 3.2.7 when an interrupt is received ................................................................................................. 21 chapter 4 program memory (rom) .......................................................................................... 23 4.1 program memory configuration ............................................................................................. 23 4.2 program memory usage ............................................................................................................... 24 4.2.1 flow of the program .................................................................................................................. 24 4.2.2 table reference ......................................................................................................................... 27 chapter 5 data memory (ram) .................................................................................................... 31 5.1 data memory configuration ....................................................................................................... 31 5.1.1 system register (sysreg) ..................................................................................................... 32 5.1.2 data buffer (dbf) ...................................................................................................................... 32 5.1.3 general register (gr) .............................................................................................................. 33 5.1.4 port registers ............................................................................................................................ 33 5.1.5 general data memory ............................................................................................................... 34 5.1.6 unmounted data memory ......................................................................................................... 34 - ii - chapter 6 stack .............................................................................................................................. 3 5 6.1 stack configuration ...................................................................................................................... 35 6.2 functions of the stack ................................................................................................................ 35 6.3 address stack registers (asrs) ............................................................................................... 36 6.4 interrupt stack registers (intsks) ........................................................................................ 36 6.5 stack pointer (sp) and interrupt stack registers ........................................................ 37 6.6 stack operation ............................................................................................................................... 38 6.6.1 on execution of instructions call, ret, retsk ................................................................... 38 6.6.2 table reference (movt dbf, @ar instruction) ..................................................................... 38 6.6.3 operation on execution of interrupt receipt and reti instruction ......................................... 39 6.7 stack nesting levels and the push and pop instructions ......................................... 39 chapter 7 system register (sysreg) .................................................................................... 41 7.1 system register configuration ............................................................................................... 41 7.2 address register (ar) ................................................................................................................... 43 7.2.1 address register configuration ................................................................................................ 43 7.2.2 address register functions ...................................................................................................... 43 7.3 window register (wr) .................................................................................................................... 45 7.3.1 window register configuration ................................................................................................ 45 7.3.2 window register functions ...................................................................................................... 45 7.4 bank register (bank) ..................................................................................................................... 46 7.4.1 bank register configuration ..................................................................................................... 46 7.4.2 functions of bank register ....................................................................................................... 46 7.5 index register (ix) and data memory row address pointer (memory pointer: mp) ...................................................................................................................... 47 7.5.1 index register (ix) .................................................................................................................... 47 7.5.2 data memory row address pointer (memory pointer: mp) .................................................... 47 7.5.3 ixe = 0 and mpe = 0 (no data memory modification) ........................................................... 49 7.5.4 ixe = 0 and mpe = 1 (diagonal indirect data transfer) ......................................................... 51 7.5.5 ixe = 1 and mpe = 0 (index modification) ............................................................................... 53 7.6 general register pointer (rp) .................................................................................................. 57 7.6.1 general register pointer configuration ................................................................................... 57 7.6.2 functions of the general register pointer ............................................................................... 58 7.7 program status word (psword) ............................................................................................... 59 7.7.1 program status word configuration ......................................................................................... 59 7.7.2 functions of the program status word .................................................................................... 60 7.7.3 index enable flag (ixe) ............................................................................................................ 61 7.7.4 zero flag (z) and compare flag (cmp) .................................................................................. 61 7.7.5 carry flag (cy) ......................................................................................................................... 61 7.7.6 binary-coded decimal flag (bcd) ........................................................................................... 62 7.7.7 notes concerning use of arithmetic operations ..................................................................... 62 7.8 notes concerning use of the system register ............................................................... 63 7.8.1 reserved words for the system register ................................................................................ 63 7.8.2 handling of system register addresses fixed at 0 ................................................................ 65 - iii - chapter 8 general register (gr) ........................................................................................... 67 8.1 general register configuration ............................................................................................ 67 8.2 functions of the general register ....................................................................................... 67 chapter 9 register file (rf) ...................................................................................................... 69 9.1 register file configuration ...................................................................................................... 69 9.1.1 configuration of the register file ............................................................................................. 69 9.1.2 relationship between the register file and data memory ..................................................... 69 9.2 functions of the register file ................................................................................................. 70 9.2.1 functions of the register file ................................................................................................... 70 9.2.2 functions of control register ................................................................................................... 70 9.2.3 register file manipulation instructions .................................................................................... 71 9.3 control register ............................................................................................................................ 72 9.4 notes concerning use of the register file ....................................................................... 73 9.4.1 notes concerning operation of the control register (read-only and unused registers) ... 73 9.4.2 register file symbol definitions and reserved words ........................................................... 73 chapter 10 data buffer (dbf) ................................................................................................... 77 10.1 data buffer configuration ........................................................................................................ 77 10.2 functions of the data buffer ................................................................................................... 78 10.2.1 data buffer and peripheral hardware ...................................................................................... 79 10.2.2 data transfer with peripheral hardware .................................................................................. 80 10.2.3 table reference ......................................................................................................................... 81 chapter 11 arithmetic and logic unit (alu) ....................................................................... 83 11.1 alu block configuration ............................................................................................................ 83 11.2 functions of the alu block ....................................................................................................... 83 11.2.1 functions of the alu ................................................................................................................. 83 11.2.2 functions of temporary registers a and b .............................................................................. 88 11.2.3 functions of the status flip-flop ............................................................................................... 88 11.2.4 operations in 4-bit binary ......................................................................................................... 89 11.2.5 operations in bcd ..................................................................................................................... 89 11.2.6 operations in the alu block ..................................................................................................... 90 11.3 arithmetic operations (addition and subtraction in 4-bit binary and bcd) ....... 91 11.3.1 addition and subtraction when cmp = 0 and bcd = 0 .......................................................... 91 11.3.2 addition and subtraction when cmp = 1 and bcd = 0 .......................................................... 91 11.3.3 addition and subtraction when cmp = 0 and bcd = 1 .......................................................... 92 11.3.4 addition and subtraction when cmp = 1 and bcd = 1 .......................................................... 92 11.3.5 notes concerning use of arithmetic operations ..................................................................... 92 11.4 logical operations ........................................................................................................................ 93 11.5 bit judgements ............................................................................................................................... .. 94 11.5.1 true (1) bit judgement ........................................................................................................... 94 11.5.2 f alse (0) bit judgement ......................................................................................................... 95 - iv - 11.6 comparison judgements .............................................................................................................. 96 11.6.1 equal to judgement ................................................................................................................ 96 11.6.2 not equal to judgement ......................................................................................................... 97 11.6.3 greater than or equal to judgement .................................................................................... 97 11.6.4 less than judgement ............................................................................................................ 98 11.7 rota tions ............................................................................................................................... .............. 99 11.7.1 rotation to the right ................................................................................................................. 99 11.7.2 rotation to the left .................................................................................................................. 100 chapter 12 ports ......................................................................................................................... 101 12.1 port 0a (p0a 0 , p0a 1 , p0a 2 , p0a 3 ) .................................................................................................... 101 12.2 port 0b (p0b 0 , p0b 1 , p0b 2 , p0b 3 ) .................................................................................................... 102 12.3 port 0c (p0c 0 /adc 0 , p0c 1 /adc 1 , p0c 2 /adc 2 , p0c 3 /adc 3 ) .......................................................... 103 12.4 port 0d (p0d 0 /sck, p0d 1 /so, p0d 2 /si, p0d 3 /tm0out) ................................................................ 104 12.5 port 1a (p1a 0 , p1a 1 , p1a 2 , p1a 3 ) .................................................................................................... 105 12.6 port 1b (p1b 0 ) .............................................................................................................................. ...... 105 12.7 port control register ............................................................................................................... 106 12.7.1 input/output switching by group i/o ...................................................................................... 106 12.7.2 input/output switching by bit i/o ........................................................................................... 107 12.7.3 specifying pull-up resistor incorporation using software ................................................... 109 chapter 13 peripheral hardware ......................................................................................... 111 13.1 8-bit timers/counters (tm0 and tm1) ........................................................................................ 111 13.1.1 8-bit timers/counters configuration ....................................................................................... 111 13.1.2 operation of 8-bit timers/counters ........................................................................................ 115 13.1.3 selecting count pulse ............................................................................................................. 115 13.1.4 setting count value to modulo register ................................................................................ 116 13.1.5 reading value of count register ........................................................................................... 117 13.1.6 setting of interval time ........................................................................................................... 118 13.1.7 error of interval time ............................................................................................................... 119 13.1.8 timer 0 output ......................................................................................................................... 121 13.2 basic interval timer (btm) ......................................................................................................... 122 13.2.1 basic interval timer configuration .......................................................................................... 122 13.2.2 registers controlling basic interval timer ............................................................................. 123 13.2.3 operation of basic interval timer ........................................................................................... 124 13.2.4 watchdog timer function ....................................................................................................... 125 13.3 a/d converter ............................................................................................................................... .. 128 13.3.1 a/d converter configuration ................................................................................................... 128 13.3.2 functions of a/d converter ..................................................................................................... 129 13.3.3 setting values in the 8-bit data register (adcr) ................................................................. 132 13.3.4 reading values from the 8-bit data register (adcr) .......................................................... 133 13.3.5 a/d converter operation ......................................................................................................... 134 13.4 serial interface (sio) .................................................................................................................. 141 13.4.1 functions of the serial interface ............................................................................................. 141 13.4.2 3-wire serial interface operation modes ................................................................................ 143 13.4.3 setting values in the shift register ........................................................................................ 147 13.4.4 reading values from the shift register ................................................................................. 148 - v - chapter 14 interrupt functions ............................................................................................ 149 14.1 interrupt source types and vector addresses ............................................................ 150 14.2 hardware components of the interrupt control circuit ....................................... 151 14.3 interrupt sequence ..................................................................................................................... 158 14.3.1 receiving an interrupt ............................................................................................................. 158 14.3.2 return from the interrupt routine ........................................................................................... 159 14.3.3 interrupt accepting timing ...................................................................................................... 160 14.4 multi-interrupt ............................................................................................................................... 163 14.5 program example of interrupt ............................................................................................. 164 chapter 15 ac zero cross detection .................................................................................. 167 chapter 16 standby function .................................................................................................. 169 16.1 overview of the standby function ....................................................................................... 169 16.2 halt mode ............................................................................................................................... ........... 170 16.2.1 setting halt mode ................................................................................................................. 170 16.2.2 start address after halt mode is released ......................................................................... 170 16.2.3 halt mode setting conditions ............................................................................................... 172 16.3 stop mode ............................................................................................................................... ........... 174 16.3.1 setting of stop mode ............................................................................................................ 174 16.3.2 start address after stop mode is released ........................................................................ 174 16.3.3 stop mode setting conditions .............................................................................................. 176 chapter 17 reset ........................................................................................................................... 179 17.1 reset function ............................................................................................................................... . 180 17.2 resetting ............................................................................................................................... ............ 181 17.3 power-on/power-down reset function .............................................................................. 182 17.3.1 conditions required to enable the power-on reset function ............................................. 182 17.3.2 power-on reset function and operation .............................................................................. 183 17.3.3 condition required for use of the power-down reset function .......................................... 185 17.3.4 power-down reset function and operation .......................................................................... 185 chapter 18 one-time prom writing/verifying .................................................................... 189 18.1 differences between mask rom version and one-time prom model ..................... 189 18.2 operation mode when program memory is written/verified ................................... 190 18.3 writing procedure of program memory ........................................................................... 191 18.4 reading procedure of program memory .......................................................................... 192 chapter 19 instruction set ...................................................................................................... 193 19.1 overview of the instruction set ........................................................................................... 193 19.2 legend ............................................................................................................................... .................. 194 19.3 list of the instruction set ....................................................................................................... 195 19.4 assembler (as17k) embedded macro instructions ........................................................ 197 - vi - 19.5 instructions ............................................................................................................................... ..... 198 19.5.1 addition instructions ................................................................................................................ 198 19.5.2 subtraction instructions ........................................................................................................... 209 19.5.3 logical operation instructions ................................................................................................ 216 19.5.4 judgment instructions ............................................................................................................. 221 19.5.5 comparison instructions .......................................................................................................... 223 19.5.6 rotation instructions ................................................................................................................ 226 19.5.7 transfer instructions ................................................................................................................ 227 19.5.8 branch instructions .................................................................................................................. 243 19.5.9 subroutine instructions ............................................................................................................ 246 19.5.10 interrupt instructions ................................................................................................................ 251 19.5.11 other instructions .................................................................................................................... 253 chapter 20 assembler reserved words ............................................................................ 255 20.1 mask option directive ................................................................................................................. 255 20.1.1 specifying mask option .......................................................................................................... 255 20.2 reserved symbols ......................................................................................................................... 257 appendix a development of m pd171 subseries ............................................................. 261 appendix b comparison of functions between m pd17135a, 17137a, and m pd17145 subseries ................................................................................................ 263 appendix c development tools .............................................................................................. 265 appendix d notes on configuration of system clock oscillation circuit ...... 267 appendix e instruction list ...................................................................................................... 269 e.1 instruction list (by function) ...................................................................................................... 269 e.2 iinstruction list (alphabetical order) ......................................................................................... 270 appendix f ordering mask rom ............................................................................................... 271 - vii - list of figures (1/3) figure no. title page 3-1 program counter ............................................................................................................................... ....... 17 3-2 value of the program counter after instruction execution .................................................................... 18 3-3 value in the program counter after reset ............................................................................................. 18 3-4 value in the program counter during execution of a br addr instruction ........................................... 18 3-5 value in the program counter during execution of an indirect branch instruction .............................. 19 3-6 value in the program counter during execution of a call addr .......................................................... 19 3-7 value in the program counter during execution of an indirect subroutine call .................................. 20 3-8 value in the program counter during execution of a return instruction .............................................. 20 4-1 program memory map for the m pd17134a subseries ........................................................................... 23 4-2 call addr instruction .............................................................................................................................. 2 6 4-3 table reference (movt dbf, @ar) ...................................................................................................... 27 5-1 data memory configuration ..................................................................................................................... 31 5-2 system register configuration ................................................................................................................ 32 5-3 data buffer configuration ........................................................................................................................ 32 5-4 general register (gr) configuration ...................................................................................................... 33 5-5 port register configuration ..................................................................................................................... 33 6-1 stack configuration ............................................................................................................................... ... 35 7-1 allocation of system register in data memory ...................................................................................... 41 7-2 system register configuration ................................................................................................................ 42 7-3 address register configuration .............................................................................................................. 43 7-4 address register used as a peripheral circuit ...................................................................................... 44 7-5 window register configuration ............................................................................................................... 45 7-6 example of window register operation ................................................................................................. 45 7-7 bank register configuration ................................................................................................................... 46 7-8 index register configuration ................................................................................................................... 47 7-9 modification of data memory address by index register and memory pointer ................................... 48 7-10 operation example when ixe = 0 and mpe = 0 ................................................................................... 50 7-11 operation example when ixe = 0 and mpe = 1 ................................................................................... 52 7-12 operation example when ixe = 1 and mpe = 0 ................................................................................... 54 7-13 operation example when ixe = 1 and mpe = 0 ................................................................................... 55 7-14 operation example when ixe = 1 and mpe = 0 (array processing) ................................................... 56 7-15 general register pointer configuration .................................................................................................. 57 7-16 general register configuration ............................................................................................................... 58 7-17 program status word configuration ....................................................................................................... 59 7-18 outline of functions of the program status word ................................................................................. 60 8-1 general register configuration ............................................................................................................... 68 - viii - 9-1 register file configuration ...................................................................................................................... 69 9-2 relationship between the register file and data memory ................................................................... 70 9-3 accessing the register file using the peek and poke instructions .................................................. 72 9-4 control register configuration ................................................................................................................ 75 10-1 allocation of the data buffer ................................................................................................................... 77 10-2 data buffer configuration ........................................................................................................................ 77 10-3 relationship between the data buffer and peripheral hardware ......................................................... 78 11-1 alu configuration ............................................................................................................................... ..... 84 12-1 input/output switching by group i/o .................................................................................................... 106 12-2 port control register of bit i/o ............................................................................................................. 107 12-3 specifying pull-up resistor incorporation using software .................................................................. 109 13-1 configuration of the 8-bit timer counters ............................................................................................ 112 13-2 timer 0 mode register .......................................................................................................................... 113 13-3 timer 1 mode register .......................................................................................................................... 114 13-4 setting count value to modulo register ............................................................................................... 116 13-5 reading count value of count register ............................................................................................... 117 13-6 error when count register is cleared to 0 during counting ............................................................. 119 13-7 error when counting is started from count stop status .................................................................... 120 13-8 timer 0 output setting register ............................................................................................................ 121 13-9 basic interval timer configuration ........................................................................................................ 122 13-10 btm mode register ............................................................................................................................... 123 13-11 w atchdog timer mode register ............................................................................................................ 124 13-12 timing chart of watchdog timer (with wdtres flag used) ............................................................. 126 13-13 block diagram of the a/d converter ..................................................................................................... 128 13-14 a/d converter control register ............................................................................................................ 130 13-15 setting a value in the 8-bit data register (adcr) .............................................................................. 132 13-16 reading values from the 8-bit data register (adcr) ......................................................................... 133 13-17 relationship between the analog input voltage and digital conversion result ................................ 134 13-18 using the successive mode for the a/d converter .............................................................................. 136 13-19 a/d conversion timing in the continuous mode ................................................................................. 137 13-20 using the single mode for the a/d converter ...................................................................................... 139 13-21 single mode operation (comparison) timing ...................................................................................... 140 13-22 block diagram of the serial interface ................................................................................................... 142 13-23 timing of 8-bit transmission and reception mode (simultaneous transmission and reception) .. 143 13-24 timing of the clock synchronization 8-bit reception mode (so pin output high impedance) ........ 144 13-25 serial interface control register ........................................................................................................... 145 13-26 setting a value in the shift register ..................................................................................................... 147 13-27 reading a value from the shift register .............................................................................................. 148 list of figures (2/3) figure no. title page - ix - 14-1 interrupt control register ...................................................................................................................... 152 14-2 interrupt processing procedure ............................................................................................................ 158 14-3 return from interrupt processing .......................................................................................................... 159 14-4 interrupt accepting timing (when inte = 1, ip = 1) ..................................................................... 160 14-5 example of multi-interrupt ..................................................................................................................... 163 15-1 block diagram for the ac zero cross detector ................................................................................... 167 15-2 zero cross detection signal ................................................................................................................. 168 16-1 releasing halt mode ........................................................................................................................... 171 16-2 releasing stop mode .......................................................................................................................... 175 17-1 reset block configuration ..................................................................................................................... 181 17-2 reset operation ............................................................................................................................... ...... 181 17-3 example of the power-on reset operation ......................................................................................... 184 17-4 example of the power-down reset operation ..................................................................................... 186 17-5 example of reset operation during the period from power-down reset to power recovery ......... 187 18-1 procedure of program memory writing ................................................................................................ 191 18-2 procedure of program memory reading .............................................................................................. 192 d-1 external circuit of system clock oscillation circuit ............................................................................. 267 d-2 example of incorrect oscillation circuits .............................................................................................. 268 list of figures (3/3) figure no. title page - x - list of tables (1/2) table no. title page 2-1 processing of unused pins ..................................................................................................................... 14 4-1 program memory configuration .............................................................................................................. 23 4-2 vector address for the m pd17134a subseries ...................................................................................... 24 6-1 operation of stack pointer ...................................................................................................................... 37 6-2 operation of the instructions call, ret, and retsk .......................................................................... 38 6-3 stack operation during table reference ................................................................................................ 38 6-4 operation during interrupt receipt and reti instruction ...................................................................... 39 6-5 stack operation during the push and pop instructions ...................................................................... 39 7-1 specifying the bank in data memory ...................................................................................................... 46 7-2 instructions subject to address modification .......................................................................................... 48 7-3 zero flag (z) and compare flag (cmp) ................................................................................................ 61 10-1 peripheral hardware ............................................................................................................................... .79 11-1 list of alu instructions ............................................................................................................................ 86 11-2 results of arithmetic operations performed in 4-bit binary and bcd .................................................. 89 11-3 t ypes of arithmetic operations ............................................................................................................... 91 11-4 logical operations ............................................................................................................................... .... 93 11-5 table of true v alues for logical operations .......................................................................................... 93 11-6 bit judgement instructions ...................................................................................................................... 94 11-7 comparison judgement instructions ....................................................................................................... 96 12-1 writing into and reading from the port register (0.70h) .................................................................... 101 12-2 writing into and reading from the port register (0.71h) .................................................................... 102 12-3 switching the port and a/d converter .................................................................................................. 103 12-4 register file contents and pin functions ............................................................................................ 104 12-5 contents read from the port register (0.73h) .................................................................................... 105 12-6 writing into and reading from the port register (1.70h) .................................................................... 105 13-1 data conversion time for the a/d converter ....................................................................................... 138 13-2 serial clock list ............................................................................................................................... ...... 141 13-3 operating mode of the serial interface ................................................................................................. 143 14-1 interrupt source types .......................................................................................................................... 150 14-2 interrupt request flag and interrupt enable flag ................................................................................ 151 16-1 status in standby mode ........................................................................................................................ 169 16-2 halt mode release condition ............................................................................................................. 170 16-3 start address after halt mode is released ........................................................................................ 170 16-4 stop mode release condition ............................................................................................................ 174 16-5 start address after stop mode is released ....................................................................................... 174 - xi - list of tables (2/2) table no. title page 17-1 hardware status at reset ..................................................................................................................... 180 18-1 pins used for writing/verifying program memory ................................................................................ 189 18-2 differences between mask rom version and one-time prom version .......................................... 190 18-3 setting operation modes ....................................................................................................................... 190 20-1 mask option definition directive ........................................................................................................... 256 - xii - [memo] chapter 1 general description the m pd17134a subseries is a 4-bit single-chip microcontroller employing the 17k architecture and containing an 8-bit a/d converter (4 channels), a timer (3 channels), an ac zero cross detector, a power-on reset circuit, and a serial interface. the m pd17p136a and 17p137a are the one-time prom version of the m pd17136a and 17137a, respectively, and are suitable for program evaluation at system development and for small-scale production. the following are features of the m pd17134a subseries. ? 17k architecture: general-purpose register mode, instruction length: fixed to 16 bits ? instruction execution time: 2 m s (f x = 8 mhz, ceramic oscillation) 8 m s (f cc = 2 mhz, rc oscillation) ? program memory: m pd17134a : 2k bytes (1024 16 bits) m pd17135a : 2k bytes (1024 16 bits) m pd17136a : 4k bytes (2048 16 bits) m pd17137a : 4k bytes (2048 16 bits) m pd17p136a : 4k bytes (2048 16 bits, one-time prom) m pd17p137a : 4k bytes (2048 16 bits, one-time prom) ? data memory (ram): 112 4 bits ? a/d converter: 4 channels (8-bit resolution, successive approximation type) ? timer: 3 channels (8-bit timer/counter 2 channels, basic interval timer note ) ? serial interface: 1 channel (clocked 3-wire mode) ? supply voltage: v dd = 4.5 to 5.5 v (f x = 400 khz to 8 mhz) v dd = 2.7 to 5.5 v (f x = 400 khz to 4 mhz) v dd = 2.7 to 5.5 v (f cc = 400 khz to 2 mhz) for m pd17134a and 17136a note an internal reset signal can be generated by using the basic interval timer (watchdog timer function). these features of the m pd17134a subseries are suitable for use as a controller or a slave device in the following application fields; ? electronic thermos bottle ? rice cooker ? audio equipment ? battery charger ? printer ? plain paper copier 1 1 chapter 1 general description 2 1.1 function list item m pd17134a m pd17135a m pd17136a m pd17137a m pd17p136a m pd17p137a rom configuration mask rom one-time prom rom capacity 2kb (1024 5 16 bits) 4kb (2048 5 16 bits) ram capacity 112 5 4 bits stack address stack 5, interrupt stack 3 number of i/o port ? i/o : 20 22 ? input only : 1 ? sensor input note : 1 a/d converter 8-bit resolution 4 channels (shared with port pin), absolute precision 1.5 lsb or less timer 3 channels ? 8-bit timer counter : 2 channels (16-bit timer 1 channel applicable) ? 7-bit basic interval timer : 1 channel (watchdog timer applicable) serial interface 1 channel (3 wires) ac zero cross detection provided (can be used in application circuit at v dd = 5 v 10%) function interrupt ? nesting by hardware (up to 3 levels) rising edge detection ? external interrupts (int) : 1 falling edge detection selectable both rising and falling edges detection ? timer 0 (tm0) ? internal interrupts : 1 ? timer 1 (tm1) ? basic interval timer (btm) ? serial interface (sio) system clock rc ceramic rc ceramic rc ceramic oscillation oscillation oscillation oscillation oscillation oscillation instruction 8 m s2 m s8 m s2 m s8 m s2 m s execution time at f x = 2 mhz at f x = 8 mhz at f x = 2 mhz at f x = 8 mhz at f x = 2 mhz at f x = 8 mhz standby halt, stop power-on/ available (effective only for application circuit with v dd = 5 v 10 %, 400 khz to 4 mhz) power-down reset supply voltage v dd = 2.7 to 5.5 v (5 v 10 % when using a/d converter) package 28-pin plastic shrink dip, 28-pin plastic sop note the int pin can be used as an input pin (sense input) when the external interrupt function is not used. the sense input function is to read the status of the pin by using the int flag of a control register, instead of a port register. caution the prom model is highly compatible with the mask rom model in terms of functions but its internal rom circuit and electrical characteristics are partially different from those of the mask rom model. to replace the prom model with the mask rom model, thoroughly evaluate the application by using a sample of the mask rom model. chapter 1 general description 3 1.2 ordering information part number package internal rom m pd17134act- 28-pin plastic shrink dip (400 mil) mask rom m pd17135act- 28-pin plastic shrink dip (400 mil) mask rom m pd17136act- 28-pin plastic shrink dip (400 mil) mask rom m pd17137act- 28-pin plastic shrink dip (400 mil) mask rom m pd17p136act 28-pin plastic shrink dip (400 mil) one-time prom m pd17p137act 28-pin plastic shrink dip (400 mil) one-time prom m pd17134agt- 28-pin plastic sop (375 mil) mask rom m pd17135agt- 28-pin plastic sop (375 mil) mask rom m pd17136agt- 28-pin plastic sop (375 mil) mask rom m pd17137agt- 28-pin plastic sop (375 mil) mask rom m pd17p136agt 28-pin plastic sop (375 mil) one-time prom m pd17p137agt 28-pin plastic sop (375 mil) one-time prom remark : rom code number chapter 1 general description 4 1.3 block diagram remarks 1. the terms cmos and n-ch in square brackets indicate the output form of the port. cmos : cmos push-pull output n-ch : n-channel open-drain output (each pin can contain pull-up resistor bit-wise as specified using a mask option.) 2. the devices in parentheses are effective only in the case of program memory write/verify mode of the m pd17p136a and m pd17p137a. notes 1. the rom (or prom) capacity of each product is as follows: 1024 16 bits : m pd17134a, 17135a 2048 16 bits : m pd17136a, 17137a, 17p136a, 17p137a 2. the stack capacity of each product is as follows: 5 10 bits : m pd17134a, 17135a 5 11 bits : m pd17136a, 17137a power-on/ power-down reset v dd p0a 0 p0a 1 p0a 2 p0a 3 alu rom/ one-time prom program counter stack note2 p0a (cmos) clock divider system clock generator x in x out f x / 2 n cpu clock clk stop p0b 0 p0b 1 p0b 2 p0b 3 p0c 0 /adc 0 p0c 1 /adc 1 p0c 2 /adc 2 p0c 3 /adc 3 p0d 0 /sck p0d 1 /so p0d 2 /si p0d 3 /tm0out p1a 0 p1a 1 p1a 2 p1a 3 p1b 0 reset ram 112 4 bits rf system reg. p0b (cmos) p0c (cmos) a/d con- verter p0d (n-ch) serial inter- face instruction decoder p1a (n-ch) p1b timer 0 timer 1 irqtm0 irqtm1 irqbtm basic interval timer interrupt controller irqtm0 irqtm1 irqbtm irqsio ac zerocross detector int tm0 irqsio gnd f x /2 n f x /2 n f x /2 n (v pp ) (clk) note2 note1 chapter 1 general description 5 1.4 pin configuration (top view) (1) normal operating mode 28-pin plastic shrink dip (400 mil) m pd17134act- , m pd17135act- , m pd17136act- , m pd17137act- m pd17p136act- , m pd17p137act- 28-pin plastic sop (375 mil) m pd17134agt- , m pd17135agt- , m pd17136agt- , m pd17137agt- m pd17p136agt- , m pd17p137agt- adc 0 to adc 3 : analog input for the a/d converter gnd : ground int : external interrupt input osc 0 , osc 1 : system clock oscillation p0a 0 to p0a 3 : port 0a p0b 0 to p0b 3 : port 0b p0c 0 to p0c 3 : port 0c p0d 0 to p0d 3 : port 0d p1a 0 to p1a 3 : port 1a p1b 0 : port 1b reset : reset input sck : serial clock input/output si : serial data input so : serial data output tm0out : timer 0 carry output v adc : analog power supply v dd : power supply x in , x out : system clock oscillation v adc 1 int 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 p0c 3 /adc 3 p0c 2 /adc 2 p0c 1 /adc 1 p0c 0 /adc 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 gnd reset p1a 0 p1a 1 p1a 2 p1a 3 p1b 0 x in (osc 1 ) p0d 0 /sck x out (osc 0 ) p0d 1 /so p0d 2 /si p0d 3 /tm0out v dd chapter 1 general description 6 (2) program memory write/verify mode 28-pin plastic shrink dip (400 mil) m pd17p136act, 17p137act 28-pin plastic sop (375 mil) m pd17p136agt, 17p137agt caution ( ) represents processing of the pins which are not used in program memory write/verify mode. l : connect to gnd via pull-down resistor one by one. reset : set the same electric potential as v dd in program memory write/verify mode. reset pin is also used for system reset input before setting program memory write/verify mode. therefore, reset pin should be set to the same electric potential as v dd 10 m s or later than that of v dd pin (for details, refer to chapter 18 one-time prom writing/verifying). open : do not connect anything. v dd : connect to v dd directly. (v dd ) 1 (l) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 md 3 md 2 md 1 md 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 gnd reset v pp clk v dd (l) (open) chapter 1 general description 7 clk : clock input for address updating d 0 -d 7 : data input/output gnd : ground md 0 -md 3 : operation mode select reset : reset input v dd : power supply v pp : program voltage application [memo] 8 pin no. pin name function output at reset 1v adc supplies power and reference voltage for the a/d converter 2 p0c 3 /adc 3 /md 3 note1 constitute port 0c, serve as analog input pins of a/d cmos input | | converter, or select operating mode when program memory push-pull (p0c) 5 p0c 0 /adc 0 /md 0 note1 is written or verified. ? p0c 3 to p0c 0 ? 4-bit input/output port ? input/output setting in 1-bit unit ? adc 3 to adc 0 ? analog input for the a/d converter ? md 3 to md 0 ? available for the m pd17p136a and m pd17p137a only ? selects operating mode at program memory writing/ verification 6 p0b 3 /d 7 note1 used as port 0b, or data input/output pins in program cmos input | | memory write/verify mode. push-pull (p0b) 9 p0b 0 /d 4 note1 ? p0b 3 to p0b 0 ? 4-bit input/output port ? input/output setting in 4-bit unit ? software-selectable pull-up resistor ? d 7 to d 4 ? available for the m pd17p136a and m pd17p137a only ? 8-bit data input/output at program memory writing/ verification 10 p0a 3 /d 3 note1 used as port 0a, or data input/output pin in program memory cmos input | | write/verify mode. push-pull (p0a) 13 p0a 0 /d 0 note1 ? p0a 3 to p0a 0 ? 4-bit input/output port ? input/output setting in 4-bit unit ? software-selectable pull-up resistor ? d 3 to d 0 ? available for the m pd17p136a and m pd17p137a only ? 8-bit data input/output at program memory writing/ verification 14 gnd ground 15 int external interrupt request input or sensor signal input input 16 reset system reset input pin input a pull-up resistor can be internally connected by mask option note2 notes 1. the md 0 -md 3 and d 0 -d 7 pins are valid with the m pd17p136a and 17p137a only. 2. the m pd17p136a and 17p137a do not have a pull-up resistor connected by mask option. chapter 2 pin functions 2.1 pin functions 9 chapter 2 pin functions 10 pin no. pin name function output at reset 17 p1b 0 /v pp note1 used as port 1b, or programming voltage supply pin in input input program memory write/verify mode. ? p1b 0 ? 1-bit input port ? a pull-up resistor can be internally connected by mask option note2 ? v pp ? available for the m pd17p136a and m pd17p137a only ? applies programming voltage (+12.5 v) at program memory writing/verification 18 p1a 3 port 1a n-ch open input | | ? 4-bit input/output port drain 21 p1a 0 ? input/output setting in 4-bit unit ? a pull-up resistor can be internally connected by mask option note2 22 p0d 3 /tm0out used as port 0d, or timer 0 carry output, serial data input, n-ch open input serial data output, and serial clock input/output pins drain a pull-up resistor can be internally connected by mask option note2 ? p0d 3 to p0d 0 ? 4-bit input/output port ? input/output setting in 1 bit unit ? tm0out ? timer 0 carry output 23 p0d 2 /si ? si ? serial data input 24 p0d 1 /so ? so ? serial data output 25 p0d 0/ sck ? sck ? serial clock input/output 26 x out in the case of the m pd17135a/17137a/17p137a 27 x in /clk note3 ? x in , x out ? connected to a resonator for system clock oscillation ? the ceramic resonator is connected. ? clk ? available for the m pd17p137a only ? clock input pin for address updating at program memory writing/verification 26 osc 0 in the case of the m pd17134a/17136a/17p136a 27 osc 1 /clk note3 ? osc 0 , osc 1 ? connected to a resonator for system clock oscillation ? resistor is connected between osc 0 and osc 1 . ? clk ? available for the m pd17p136a only ? clock input pin for address updating at program memory writing/verification 28 v dd power supply in the program memory write/verify mode of the m pd17p136a/17p137a, +6 v is applied. notes 1. the v pp pin is valid only with the m pd17p136a and 17p137a. 2. the m pd17p136a and 17p137a do not have a pull-up resistor connected by mask option. 3. the clk pin is valid only with the m pd17p136a and 17p137a. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 chapter 2 pin functions 11 2.2 pin input/output circuit below are simplified diagrams of the input/output circuits for each pin. (1) p0a 0 -p0a 3 , p0b 0 -p0b 3 (2) p0c 0 /adc 0 - p0c 3 /adc 3 data v dd p-ch n-ch output disable output latch selector v dd pull-up flag input buffer p-ch data v dd p-ch n-ch output disable output latch selector input buffer a/d converter input disable chapter 2 pin functions 12 (3) p0d 0 -p0d 3 , p1a 0 -p1a 3 note the m pd17p136a and 17p137a do not have a pull-up resistor as mask option. (4) p1b 0 note the m pd17p136a and 17p137a do not have a pull-up resistor as mask option. data n-ch output disable output latch selector input buffer v dd mask option note input buffer v dd mask option note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 chapter 2 pin functions 13 (5) int (6) reset note the m pd17p136a and 17p137a do not have a pull-up resistor as mask option. input buffer input buffer v dd mask option note chapter 2 pin functions 14 2.3 processing of unused pins the unused pins should be handled as follows: table 2-1. processing of unused pins pin name recommended processing internal external port input mode p0a, p0b connect pull-up resistor by software open p0c connect each pin to v dd or gnd via resistor note 1 p0d, p1a pull-up resistor not connected by mask directly connect to gnd option pull-up resistor connected by mask open option p1b 0 note2 pull-up resistor not connected by mask directly connect to gnd option output mode p0a, p0b, p0c open (cmos port) p0d, p1a outputs low level without pull-up (n-ch open- resistor connected by mask option drain ports) outputs high level without pull-up resistor connected by mask option external interrupt (int) pull-up resistor not connected by mask directly connect to v dd or gnd option pull-up resistor connected by mask open option reset note3 pull-up resistor not connected by mask directly connect to v dd when only internal power-on/power- option down reset function is used pull-up resistor connected by mask option v adc directly connect to v dd notes 1. when connecting an external pull-up resistor (to v dd via resistor) or pull-down resistor (to gnd via resistor), make sure that the driving voltage and current consumption of the port are not exceeded. when connecting a pull-up or pull-down resistor with a high resistance to a port pin, make sure that noise is not superimposed on the pin. generally, the resistance of the pull-up or pull-down resistor is about several k w , though it varies depending on the application circuit. 2. because the p1b 0 pin is multiplexed with a test mode setting function, do not connect a pull-up resistor to this pin using the mask option. directly connect it to gnd. 3. in an application circuit where high reliability is required, be sure to input the reset signal from an external source. because the reset pin is multiplexed with a mode setting function, directly connect it to v dd if not use. caution it is recommended that the i/o mode, pull-up of resistors by software, and output levels of pins be fixed by repeatedly setting in each loop of the program. remark the m pd17p136a and 17p137a do not have a pull-up resistor as mask option. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 chapter 2 pin functions 15 2.4 notes on using reset pin and p1b 0 pin the reset and p1b 0 pins have a function for setting a test mode in which the internal operations of the m pd17134a subseries are tested (for ic test), in addition to the functions described in 2.1 pin functions . when a voltage exceeding v dd is applied to either of these pins, the test mode is set. this means that, even during the normal operation, the test mode is set if a noise exceeding v dd is applied. as a result, the operation may not be performed normally. this is especially true if the wiring length of the reset or p1b 0 pin is too long in which case a noise may be superimposed on the wiring. therefore, perform wiring so that noise may not be superimposed, by keeping the wiring length as short as possible. if noise is inevitable, take noise preventive measures by using an external component as illustrated below. ? connect a diode with low v f between v dd and reset/p1b 0 ? connect a capacitor between v dd and reset/p1b 0 reset, p1b 0 v dd v dd diode with low v f reset, p1b 0 v dd v dd [memo] 16 chapter 3 program counter (pc) the program counter is used to specify an address in program memory. 3.1 program counter configuration figure 3-1 shows the configuration of the program counter. the program counters of the m pd17134a and m pd17135a are 10-bit binary counters. the program counters of the m pd17136a, m pd17137a, m pd17p136a, and m pd17p137a are 11-bit binary counters. this program counter is incremented whenever an instruction is executed. figure 3-1. program counter remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. 3.2 program counter operation normally, the program counter is automatically incremented each time a command is executed. the memory address at which the next instruction to be executed is stored is assigned to the program counter under the following conditions: at reset; when a branch, subroutine call, return, or table reference instruction is executed; or when an interrupt is received. 3.2.1 to 3.2.7 explain program counter operation during execution of each instruction. pc pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 msb lsb pc10 17 chapter 3 program counter (pc) 18 figure 3-2. value of the program counter after instruction execution remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. 3.2.1 at reset by setting the reset pin to low, the program counter is set to 0000h. figure 3-3. value in the program counter after reset remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. 3.2.2 during execution of the branch instruction (br) there are two ways to specify branching using the branch instruction. one is to specify the branch address in the operand using the direct branch instruction (br addr). the other is branch to the address specified by the address register using the indirect branch instruction (br @ar). the address specified by a br addr instruction is placed in the program counter. figure 3-4. value in the program counter during execution of a br addr instruction remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0000000000 at reset br addr call addr br @ar call @ar (movt dbf, @ar) ret retsk reti during interrupt value in the address register (ar) value set by the addr value in the address stack register location pointed to by the stack pointer (return address) vector address for the interrupt program counter value program counter bit instruction pc10 0 0 msb lsb 0 00000000 all bits are set to 0 0 pc10 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 msb lsb value specified in the direct branch instruction pc9 chapter 3 program counter (pc) 19 an indirect branch instruction causes the address in the address counter to be placed in the program counter. figure 3-5. value in the program counter during execution of a br @ar instruction remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. 3.2.3 during execution of subroutine calls (call) there are two ways to specify branching using subroutine calls. one is to specify the branch address in the operand using the direct subroutine call (call addr). the other is branch to the address specified by the address register using the indirect subroutine call (call @ar). a call addr causes the value in the program counter to be saved in the stack and then the address specified in the operand to be placed in the program counter. call addr can specify 000h-03ffh in the m pd17134a and 17135a, and 0000h-07ffh in the m pd17136a, 17137a, 17p136a, and 17p137a. figure 3-6. value in the program counter during execution of a call addr remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. a call @ar causes the value in the program counter to be saved in the stack and then the value in the address register to be placed in the program counter. pc10 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 msb lsb ar10 ar8 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 pc9 ar9 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 msb lsb address specified in the addr pc10 chapter 3 program counter (pc) 20 figure 3-7. value in the program counter during execution of an indirect subroutine call remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. 3.2.4 during execution of return instructions (ret, retsk, reti) during execution of a return instruction (ret, retsk, reti), the program counter is restored to the value saved in the address stack register. figure 3-8. value in the program counter during execution of a return instruction remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. 3.2.5 during table reference (movt) during execution of table reference (movt dbf, @ar), the value in the program counter is saved in the stack, the address register is set by the program counter, then the contents stored at that program memory location is read into the data buffer (dbf). after that, the program counter is restored to the value saved in the address stack register. one level of the address stack is temporarily used during execution of table reference. be careful of the stack level. pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 msb lsb ar9 ar8 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 pc10 ar10 (n = 0 to 4) address stack register n pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 msb lsb (n = 0 to 4) address stack register n pc10 chapter 3 program counter (pc) 21 3.2.6 during execution of skip instructions (ske, skge, sklt, skne, skt, skf) when skip conditions are met and a skip instruction (ske, skge, sklt, skne, skt, skf) is executed, the instruction immediately following the skip instruction is treated as a no operation instruction (nop). therefore, whether skip conditions are met or not, the number of instructions executed and instruction execution time remain the same. 3.2.7 when an interrupt is received when an interrupt is received, the value in the program counter is saved in the address stack. next, the vector address for the interrupt received is placed in the program counter. [memo] 22 23 chapter 4 program memory (rom) the program organization of the m pd17134a subseries is shown in table 4-1. table 4-1. program memory configuration product name program memory capacity program memory address m pd17134a 2k bytes (1024 16 bits) 0000h-03ffh m pd17135a m pd17136a m pd17137a 4k bytes (2048 16 bits) 0000h-07ffh m pd17p136a m pd17p137a program memory stores the program and the constant data table. the first area of the program memory is assigned to reset start and interrupt vector addresses. the program memory address is specified by the program counter. 4.1 program memory configuration figure 4-1 shows the program memory map. branch instructions, subroutine calls, and table references can specify any address in program memory. figure 4-1. program memory map for the m pd17134a subseries 0000h 0001h 0002h 0003h 03ffh address reset start address serial interface interrupt vector basic interval timer interrupt vector timer 1 interrupt vector subroutine entry address for the call addr instruction branch address for the br addr instruction branch address for the br @ar instruction subroutine entry address for the call @ar instruction table reference address for the movt dbf, @ar instruction 0004h 0005h external (int) interrupt vector timer 0 interrupt vector 16 bits ( pd17134a/17135a) m ( pd17136a/17137a/17p136a/17p137a) m 07ffh chapter 4 program memory (rom) 24 4.2 program memory usage program memory has the following two main functions: (1) storage of the program (2) storage of constant data the program is made up of the instructions which operate the cpu (central processing unit). the cpu executes sequential processing according to the instructions stored in the program. in other words, the cpu reads each instruction in the order stored by the program in program memory and executes it. since all instructions are 16-bit long words, each instruction is stored in a single address in program memory. constant data, such as display patterns, are set beforehand. the movt is used for reading constant data in program memory to transfer data from program memory to the data buffer (dbf) in data memory. reading the constant data in program memory is called table reference. program memory is read-only (rom: read only memory) and therefore cannot be changed by any instructions. 4.2.1 flow of the program the program is usually stored in program memory starting from address 0000h and executed sequentially one address at a time. however, if for some reason a different kind of program is to be executed, it will be necessary to change the flow of the program. in this case, the branch instruction (br instruction) is used. if the same program code is going to appear in a number of places, reproducing the code each time it needs to be used will decrease the efficiency of the program. in this case, the program should be stored in only one place in memory. then, by using the call instruction, call the same program. such a program is called a subroutine. as opposed to a subroutine, code used during normal operation is called the main routine. for cases completely unrelated to the flow of the program (in which a section of code is to be executed when a certain condition arises), the interrupt function is used. whenever a condition arises that is unrelated to the flow of the program, the interrupt function can be used to branch the program to a prechosen memory location (called a vector address). items (1) to (5) explain branching of the program using the interrupt function and instructions. (1) vector address table 4-2 shows the address to which the program is branched (vector address) when a reset or interrupt occurs. table 4-2. vector address for the m pd17134a subseries vector address cause of the interrupt 0000h reset 0001h serial interface interrupt 0002h basic interval timer interrupt 0003h timer 1 interrupt 0004h timer 0 interrupt 0005h external (int) interrupt chapter 4 program memory (rom) 25 (2) direct branch a direct branch (br addr) instruction branches a value of operand (addr) as an address. (in the case of the m pd17134a and m pd17135a, the most significant bit must be 0. if an address is specified outside of this range, an error will occur in the assembler.) a br addr instruction can be used to branch to any address in program memory. (3) indirect branch when executing an indirect branch (br @ar), the program branches to the address specified by the value stored in the address register (ar). a br @ar can be used to branch to any address in program memory. also see 7.2 address register (ar) . (4) subroutine to branch execution to a subroutine, the subroutine call (call) instruction is used. the call instruction can be used in two ways: as a direct subroutine call instruction (call addr) that causes execution to branch using the value of the operand (addr) as an address, and as an indirect subroutine call instruction (call @ar) that causes execution to branch using the contents of an address register as an address. to return from a subroutine, the ret or retsk instruction is used. by executing the ret or retsk instruction, execution is returned to the program memory address next to the one at which the call instruction was executed. when the retsk instruction is used, the first instruction after execution has returned from the subroutine is executed as a nop instruction. chapter 4 program memory (rom) 26 <1> direct subroutine call when using a direct subroutine call (call addr), the 11-bit instruction operand is used to specify a program memory address of the branched subroutine. (in the case of the m pd17134a and m pd17135a, the most significant bit must be 0. if an address is specified outside of this range, an error will occur in the assembler.) example figure 4-2. call addr instruction note the program memory of the m pd17134a and m pd17135a is address 0000h to 03ffh. <2> indirect subroutine call when using an indirect subroutine call (call @ar), the value in the address register (ar) should be an address of the called subroutine. this instruction can be used to branch any address in program memory. also see 7.2 address register (ar) . address 0000h program memory 07ffh note call sub1 ret sub1; chapter 4 program memory (rom) 27 4.2.2 table reference table reference is used to reference constant data in program memory. the table reference instruction (movt dbf, @ar) is used to store the contents of the program memory address specified by the address register in the data buffer. since each location in program memory contains 16 bits of information, the movt instruction causes 16 bits of data to be stored in the data buffer. the address register can be used to table reference any location in program memory. caution note that one level of the address stack is temporarily used when performing table reference. be sure not to exceed the stack level that can be used. also see 7.2 address register (ar) and chapter 10 data buffer (dbf). remark two instruction cycles are required to execute the table reference instruction, but this is an exception. figure 4-3. table reference (movt dbf, @ar) note this bit is fixed to 0 in the case of the m pd17134a and m pd17135a. b 15 b 4 b 5 b 6 b 7 b 8 b 9 b 14 b 13 b 12 b 11 b 10 constant data program memory ar3 ar2 ar1 ar0 address register 00000 16-bit data read table address specification b 0 b 1 b 2 b 3 dbf3 data buffer dbf2 dbf1 dbf0 note b 0 b 1 b 2 b 3 b 0 b 1 b 2 b 3 b 0 b 1 b 2 b 3 b 0 b 1 b 2 b 3 b 0 b 1 b 2 b 3 b 0 b 1 b 2 b 3 b 0 b 1 b 2 b 3 b 0 b 1 b 2 b 3 chapter 4 program memory (rom) 28 (1) constant data table example 1 shows an example of code used to reference a constant data table. example 1. program to read data in a constant data table. offset mem 0.00h ; area to store the offset address. romref: bank0 ; stores the start address of the constant data ; table in the ar register. mov ar3, #.dl.table shr 12 and 0fh mov ar2, #.dl.table shr 8 and 0fh mov ar1, #.dl.table shr 4 and 0fh mov ar0, #.dl.table and 0fh mov rph, #0 ; sets the register pointer to row address 7. mov rpl, #7 shl 1 ; add ar0, offset ; adds the offset address. addc ar1, #0 addc ar2, #0 addc ar3, #0 movt dbf, @ar ; reads the constant data. table: dw 0001h ; when offset = 0h dw 0002h dw 0004h dw 0008h dw 0010h dw 0020h dw 0040h dw 0080h dw 0100h dw 0200h dw 0400h dw 0800h dw 1000h dw 2000h dw 4000h dw 8000h ; when offset = 0fh end chapter 4 program memory (rom) 29 (2) branch address table example 2 shows an example of code used to reference a branch address table. example 2. program to branch to the address of the branch address table. offset mem 0.00h ; area to store the offset address. romref: bank0 ; stores the start address of the constant data ; table in the ar register. mov ar3, #.dl.table shr 12 and 0fh mov ar2, #.dl.table shr 8 and 0fh mov ar1, #.dl.table shr 4 and 0fh mov ar0, #.dl.table and 0fh mov rph, #0 ; sets the register pointer to row address 7. mov rpl, #7 shl 1 add ar0, offset ; adds the offset address. addc ar1, #0 movt dbf, @ar ; reads the branch address put ar, dbf ; ar ? branch address br @ar table: dw 0001h ; when offset = 0h dw 0002h dw 0004h dw 0008h dw 0010h dw 0020h dw 0040h dw 0080h dw 0100h dw 0200h ; when offset = 9h end 30 [memo] chapter 5 data memory (ram) data memory stores data such as operation and control data. data can be read from or written to data memory with an instruction during normal operation. 5.1 data memory configuration figure 5-1 shows the configuration of data memory. data memory is divided into two areas called banks: bank0 and bank1. an address is allocated to the data memory for each bank. an address consists of 4 bits of memory called a nibble. the address of data memory consists of 7 bits. the high-order 3 bits are called the row address, and the low- order 4 bits are called the column address. for example, when the address of data memory is 1ah (0011010b), the row address is 1h (001b), and the column address is ah (1010b). 5.1.1 to 5.1.6 describe functions of data memory other than its use as address space. figure 5-1. data memory configuration caution no hardware is assigned to addresses 00h through 6fh in bank1. do not use this area. if the contents of this area are read, the value is undefined. an instruction to write data to this area is invalid. 31 0123456789abcdef 0 1 2 3 4 5 6 7 dbf3 dbf2 dbf1 dbf0 p0a (4 bits) p0b (4 bits) p0c (4 bits) p0d (4 bits) bank0 system register example address 1ah of bank0 the same system register is allocated in each bank. 0123456789abcdef 0 1 2 3 4 5 6 7 p1a (4 bits) bank1 system register p1b (4 bits) fixed to 0 fixed to 0 unmounted row address column address chapter 5 data memory (ram) 32 5.1.1 system register (sysreg) the system register (sysreg) consists of the 12 nibbles allocated at addresses 74h to 7fh in data memory. the system register (sysreg) is allocated independently of the banks. this means that each bank has the same system register at addresses 74h to 7fh. figure 5-2 shows the configuration of the system register. for details, refer to chapter 7 system register (sysreg) . figure 5-2. system register configuration 5.1.2 data buffer (dbf) the data buffer consists of four nibbles allocated at addresses 0ch to 0fh in bank0 of data memory. figure 5-3 shows the configuration of the data buffer. figure 5-3. data buffer configuration data buffer (dbf) address symbol 0ch dbf3 0dh dbf2 0eh dbf1 0fh dbf0 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh address window register (wr) bank register (bank) address register (ar) general register pointer (rp) program status word (psword) data memory row address pointer (mp) index register (ix) name system register (sysreg) (symbol) chapter 5 data memory (ram) 33 5.1.3 general register (gr) the general register consists of 16 nibbles specified by an arbitrary row address in an arbitrary bank in data memory. this arbitrary row address in an arbitrary bank is specified by the register pointer (rp) in the system register (sysreg). figure 5-4 shows the configuration of the general register (gr). figure 5-4. general register (gr) configuration 5.1.4 port registers a port register consists of eight nibbles allocated at addresses 70h to 73h in each bank of the data memory. as shown in figure 5-5, the high-order 3 bits of address 71h of bank1 and all of addresses 72h and 73h of bank1 are always set to 0. figure 5-5 shows the configuration of the port registers. figure 5-5. port register configuration port register address 70h p0a 71h p0b 72h p0c 73h p0d symbol bank0 p1a p1b bank1 p 0 a 3 p 0 a 2 p 0 a 1 p 0 a 0 p 0 b 3 p 0 b 2 p 0 b 1 p 0 b 0 p 0 c 3 p 0 c 2 p 0 c 1 p 0 c 0 p 0 d 3 p 0 d 2 p 0 d 1 p 0 d 0 p 1 a 3 p 1 a 2 p 1 a 1 p 1 a 0 p 1 b 0 fixed to 0 fixed to 0 fixed to 0 sysreg port register 0 1 2 3 4 5 6 7 sysreg port register 0 1 2 3 4 5 6 7 unmounted row address 0123456789abcdef column address bank0 bank1 general register the same register is allocated for each bank. area specifiable as general register pointed to by general register pointer (rp) in system register. note that row addresses 0 to 6 of bank1 are unmounted mem- ory locations. the register pointer (rp) should therefore not specify a row address in this area. chapter 5 data memory (ram) 34 5.1.5 general data memory general data memory is all the data memory not used by the port and system registers (sysreg). in other words, general data memory consists of 112 nibbles in bank0. 5.1.6 unmounted data memory there is no hardware mounted at addresses 00h to 6fh of bank1. any attempt to read this area will yield undefined value. writing data to this area is invalid and should therefore not be attempted. chapter 6 stack the stack is a register used to save information such as the program return address and the contents of the system register during execution of subroutine calls or interrupts. 6.1 stack configuration figure 6-1 shows the stack configuration. the stack consists of the following parts: one 3-bit binary counter stack pointer, five 10-bit ( m pd17134a, 17135a)/ 11-bit ( m pd17136a, 17137a, 17p136a, 17p137a) address stack registers, and three 6-bit interrupt stack registers. figure 6-1. stack configuration address stack register interrupt stack register address stack register 0 address stack register 1 address stack register 2 address stack register 3 address stack register 4 b 9 b 0 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 stack pointer (sp) b 2 b 1 b 0 spb 2 spb 1 spb 0 banksk0 bcdsk0 cmpsk0 cysk0 ixesk0 zsk0 0h 0h 1h 2h 3h 4h 1h 2h banksk1 bcdsk1 cmpsk1 cysk1 ixesk1 zsk1 banksk2 bcdsk2 cmpsk2 cysk2 ixesk2 zsk2 b 10 sp is initialized to 5h at reset remark the shaded part is effective only in the case of m pd17136a/17137a/17p136a/17p137a. 6.2 functions of the stack the stack is used to save the return address during execution of subroutine calls and table reference instructions. when an interrupt occurs, the program return address, bank register (bank), and the program status word (psword) are automatically saved in the stack. 35 chapter 6 stack 36 6.3 address stack registers (asrs) five 11-bit address stack registers (asrs) are provided as shown in figure 6-1. the functions of these registers are as follows: ? store a return address when the call addr or call @ar instruction is executed, when the first instruction cycle of the movt dbf, @ar instruction is executed, or when an interrupt is accepted. ? store the contents of an address register (ar) when the push ar instruction is executed. the asr to which the data is to be stored is specified by decrementing the value of the stack pointer (sp) by one when the instruction is executed. ? restore the contents of the asr (return address) specified by the stack pointer to the program counter and increment the value of the stack pointer by one when the ret or retsk instruction is executed, when the second instruction cycle of the movt dbf, @ar instruction is executed, or when the reti instruction is executed. ? transfer the value of the asr specified by the stack pointer to an address register and decrement the value of the stack pointer by one when the pop ar instruction is executed. caution if the stack pointer underflows as a result of executing the call addr or call @ar instruction or servicing an interrupt, it is assumed that a hang-up occurs. consequently, the internal reset signal is generated, the hardware is initialized, and the program is started from address 0000h. remark the size of the asr differs depending on the model. the m pd17134a and 17135a have five 10-bit asrs, while the m pd17136a, 17137a, 17p136a, and 17p137a have five 11-bit asrs. 6.4 interrupt stack registers (intsks) three 5-bit interrupt stack registers (intsks) are provided as shown in figure 6-1. the functions of these registers are as follows: ? five flags (bcd, cmp, cy, z, and ixe) in the program status word (psword) in the system register (sysreg) to be explained shortly are saved to the intsk when an interrupt occurs. after the flags have been saved, all the bits of the bank and psword are cleared to 0. ? the contents of intsk are restored to the psword when the reti instruction is executed. ? intsk saves data each time an interrupt has been accepted. caution if interrupts are accepted exceeding 3 levels, the first data is lost. chapter 6 stack 37 6.5 stack pointer (sp) and interrupt stack registers the stack pointer is a 3-bit binary counter that specifies the addresses of the five address stack registers as shown in figure 6-1, and is assigned to address 01h of the register file. the value of the stack pointer is initialized to 5h at reset. ? the value of sp is decremented by one when the call addr or call @ar instruction is executed, when the first instruction cycle of the movt dbf, @ar instruction is executed, or when an interrupt is accepted. ? the value of sp is incremented by one when the ret or retsk instruction is executed, when the second instruction cycle of the movt dbf, @ar instruction is executed, when the pop ar instruction is executed, or when the reti instruction is executed. when an interrupt is accepted, the counter of the interrupt stack registers is also decremented by one in addition to the sp. the value of the counter of the interrupt stack registers is incremented by one only when the reti instruction is executed. table 6-1. operation of stack pointer instruction value of stack pointer (sp) counter of interrupt stack registers call addr call @ar C1 movt, dbf @ar (1st instruction cycle) push ar not affected ret retsk +1 movt dbf, @ar (2nd instruction cycle) pop ar accepting interrupt C1 C1 reti +1 +1 remark two instruction cycles are required to execute the movt dbf, @ar instruction, but this is an exception. because the stack pointer (sp) is a 3-bit binary counter, it can take a value 0h to 7h. if the value of the stack pointer is 6 or more, however, an internal reset signal is generated (to prevent a hang-up). this is because only five address stack registers are available. because the stack pointer is located on the register file, its value can be directly read by manipulating the register file with the poke instruction. the value of the stack pointer is also changed at this time, but the values of the address stack registers are not affected. of course, the stack pointer can also be read by using the peek instruction. the value of the stack pointer is 5h at reset. chapter 6 stack 38 6.6 stack operation stack operation during execution of each instruction is explained in 6.6.1 to 6.6.3. 6.6.1 on execution of instructions call, ret, retsk table 6-2 shows operation of the stack pointer (sp), address stack register, and the program counter (pc) during execution of call, ret, and retsk. table 6-2. operation of the instructions call, ret, and retsk instruction operation call addr (1) stack pointer (sp) is decremented. call @ar (2) program counter (pc) is saved in the address stack register pointed to by the stack pointer (sp). (3) value specified by the instruction operand (addr or @ar) is transferred to the program counter. ret (1) value in the address stack register pointed to by the stack pointer (sp) is restored to the retsk program counter (pc). (2) stack pointer (sp) is incremented. when the retsk instruction is executed, the first instruction after data restoration becomes a nop instruction. 6.6.2 table reference (movt dbf, @ar instruction) table 6-3 shows the operation during table reference. table 6-3. stack operation during table reference instruction instruction cycle operation movt dbf, @ar first (1) stack pointer (sp) is decremented. (2) program counter (pc) is saved in the address stack register pointed to by the stack pointer (sp). (3) value in the address register (ar) is transferred to the program counter (pc). second (4) contents of the program memory (rom) pointed to by the program counter (pc) is transferred to the data buffer (dbf). (5) value in the address stack register pointed to by the stack pointer (sp) is restored to the program counter (pc). (6) stack pointer (sp) is incremented. caution when the movt dbf, @ar instruction is executed, one level of the address stack is temporarily used. exercise care not to exceed the usable stack level. remark two instruction cycles are required to execute the movt dbf, @ar instruction. this is an exception. chapter 6 stack 39 6.6.3 operation on execution of interrupt receipt and reti instruction table 6-4 shows stack operation during interrupt receipt and reti instruction. table 6-4. operation during interrupt receipt and reti instruction instruction operation receipt of interrupt (1) stack pointer (sp) is decremented. (2) value in the program counter (pc) is saved in the address stack register pointed to by the stack pointer (sp). (3) values in the psword flags (bcd, cmp, cy, z, ixe) are saved in the interrupt stack. (4) vector address is transferred to the program counter (pc) reti (1) values in the interrupt stack register are restored to the psword (bcd, cmp, cy, z, ixe). (2) value in the address stack register pointed to by the stack pointer (sp) is restored to the program counter (pc). (3) stack pointer (sp) is incremented. 6.7 stack nesting levels and the push and pop instructions during execution of operations such as subroutine calls and returns, the stack pointer (sp) simply functions as a 3-bit counter which is incremented and decremented by one. when the value in the stack pointer is 0h and a call or movt instruction is executed or an interrupt is received, the stack pointer is decremented to 7h. the m pd17134a subseries treat this condition as a fault and generates an internal reset signal. in order to avoid this condition, when the address stack register is being used frequently, the push and pop instructions are used to save the address stack register. table 6-5 shows stack operation during the push and pop instructions. table 6-5. stack operation during the push and pop instructions instruction operation push (1) stack pointer (sp) is decremented. (2) value in the address register (ar) is transferred to the address stack register pointed to by the stack pointer (sp). pop (1) value in the address stack register pointed to by the stack pointer (sp) is transferred to the address register (ar). (2) stack pointer (sp) is incremented. [memo] 40 chapter 7 system register (sysreg) the system register (sysreg), located in data memory, is used for direct control of the cpu. 7.1 system register configuration figure 7-1 shows the allocation address of the system register in data memory. as shown in figure 7-1, the system register is allocated in addresses 74h to 7fh of data memory, independently of the banks. this means that each bank has the same system register at addresses 74h to 7fh. since the system register is allocated in data memory, it can be manipulated using any of the data memory manipulating instructions. therefore, it is also possible to put the system register in the general register. figure 7-1. allocation of system register in data memory figure 7-2 shows the configuration of the system register. as shown in figure 7-2, the system register consists of the following seven registers. ? address register (ar) ? window register (wr) ? bank register (bank) ? index register (ix) ? data memory row address pointer (mp) ? general register pointer (rp) ? program status word (psword) system register bank1 unmounted port register port register data memory bank0 0 row address 123456789abcdef column address 0 1 2 3 4 5 6 7 0123 456789abcdef 41 chapter 7 system register (sysreg) 42 figure 7-2. system register configuration note this bit is fixed to 0 in the case of the m pd17134a and m pd17135a. 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh ixh ixm mph mpl ar3 ar2 ar1 ar0 wr bank symbol address window register (wr) bank register (bank) address register (ar) general register pointer (rp) program status word (psword) ixl rph rpl psw data memory row address pointer (mp) index register (ix) name bit m p e b c d c m p c y z i x e 00000 000 000 000 data b 3 b 2 b 1 b 0 (ix) (rp) (bank) (mp) (ar) 00000 0000000000 undefined 0000000000000000000000000000 initial value when reset 0 note b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 chapter 7 system register (sysreg) 43 7.2 address register (ar) 7.2.1 address register configuration figure 7-3 shows the configuration of the address register. as shown in figure 7-3, the address register consists of the 16 bits in address 74h to 77h (ar3 to ar0) of the system register. however, since the high-order 5 or 6 bits are always set to 0, the address register is actually 11 or 10 bits. when the system is reset, all 16 bits of the address register are reset to 0. figure 7-3. address register configuration note this bit is fixed to 0 in the case of the m pd17134a and m pd17135a. 7.2.2 address register functions the address register is used to specify an address in program memory when executing an indirect branch instruction (br @ar), indirect subroutine call (call @ar) or table reference (movt dbf, @ar). the address register can also be put on and taken off the stack by using the stack manipulation instructions (push ar, pop ar). items (1) to (4) explain address register operation during execution of each instruction. the address register can be incremented by using the dedicated increment instruction (inc ar). (1) table reference (movt dbf, @ar) when the movt dbf, @ar instruction is executed, the data in program memory (16-bit data) located at the address specified by the value in the address register is read into the data buffer (addresses 0ch to 0fh of bank0). (2) stack manipulation instructions (push ar, pop ar) when the push ar instruction is executed, the stack pointer (sp) is first decremented and then the address register is stored in the address stack pointed to by the stack pointer. when the pop ar instruction is executed, the contents of the address stack pointed to by the stack pointer is transferred to the address register and then the stack pointer is incremented. also see chapter 6 stack . b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 00 0 0 0 0000 ar1 ar0 ar2 ar3 76h 77h 75h 74h address name address register (ar) symbol bit data initial value when reset (ar) note chapter 7 system register (sysreg) 44 (3) indirect branch instruction (br @ar) when the br @ar instruction is executed, the program branches to the address in program memory specified by the value in the address register. (4) indirect subroutine call (call @ar) when the call @ar instruction is executed, the subroutine located at the address in program memory specified by the value in the address register is called. (5) address register used as a peripheral hardware register the address register can be manipulated 4 bits at a time by using data memory manipulation instructions. the address register can also be used as a peripheral hardware register for transferring 16-bit data to the data buffer. in other words, by using the put ar, dbf and get dbf ar instructions, the address register can be used to transfer 16-bit data to the data buffer. note that the data buffer is allocated in addresses 0ch to 0fh of bank0 in data memory. figure 7-4. address register used as a peripheral circuit 0123456789abcdef 0 1 2 3 4 5 6 7 dbf3 dbf2 dbf1 dbf0 ar3 ar2 ar1 ar0 system register (bank0) column address row address data buffer address register 16-bit data transfer available chapter 7 system register (sysreg) 45 7.3 window register (wr) 7.3.1 window register configuration figure 7-5 shows the configuration of the window register. as shown in figure 7-5, the window register (wr) consists of four bits allocated at address 78h of the system register. the contents of the window register is undefined after reset. however, when reset is used to release the system from halt or stop mode, the previous state is maintained. figure 7-5. window register configuration 7.3.2 window register functions the window register is used to transfer data to and from the register file (rf). data is transferred to and from the register file using the dedicated instructions peek wr, rf and poke rf, wr. (1) peek wr, rf as shown in figure 7-6, the peek wr, rf instruction is used to transfer the contents of the register file specified by rf to the window register. (2) poke rf, wr as shown in figure 7-6, the poke rf, wr instruction is used to transfer the contents of the window register to the file specified by rf. figure 7-6. example of window register operation b 3 b 2 b 1 b 0 bit symbol name address data initial value when reset 78h window register wr undefined 0123456789abcdef 0 1 2 3 4 5 6 7 system register column address row address poke instruction peek instruction wr control register register file data memory chapter 7 system register (sysreg) 46 b 3 b 2 b 1 b 0 0 000 bank 79h address name symbol bit data initial value when reset bank register (bank) 7.4 bank register (bank) 7.4.1 bank register configuration figure 7-7 shows the configuration of the bank register. the bank register consists of four bits at address 79h (bank) of the system register. however, since the three high-order bits are always set to 0, only the least significant bit is actually used. all bits are set to 0 at reset. figure 7-7. bank register configuration 7.4.2 functions of bank register the bank register is used to switch between the banks in data memory. table 7-1 shows how the banks in data memory are specified by the value in the bank register. table 7-1. specifying the bank in data memory bank register bank in data b 3 b 2 b 1 b 0 memory 0000 bank0 0001 bank1 data memory is effectively divided into two banks by the bank register. when a data memory manipulation instruction is executed, the data memory in the bank specified by the bank register is manipulated. therefore, if the current bank is bank0, in order to manipulate data memory in bank1 (port registers), the bank register must be used to switch the current bank to bank1. the system register can be manipulated regardless of the state of the bank register. for example, whether the instruction mov 78h, #0 is executed for bank0 or bank1, the effect is the same; 0 is written to address 78h of the system register. in addition, bank becomes 0 after saved to the interrupt stack register. chapter 7 system register (sysreg) 47 7.5 index register (ix) and data memory row address pointer (memory pointer: mp) 7.5.1 index register (ix) ix is used for address modification of the data memory. the difference between ix and mp is that ix modifies an address specified by a bank and operand m. ix is allocated to a total of 12 bits of system register addresses 7ah (ixh), 7bh (ixm), and 7ch (ixl), as shown in figure 7-8. actually, however, only 11 bits, the low-order 3 bits of ixh, ixm, and ixl, function as ix. an index register enable flag (ixe) which enables address modification by ix is assigned to the least significant bit of psw. when ixe = 1, the address of the data memory specified by operand m is not m, but the result of oring between m and ixm through ixl. the bank specified at this time is also indicated by oring bank and ixh. remark ixh of the m pd17134a subseries is fixed to 0, and the bank is not modified even when ixe = 1 (to prevent a bank other than 0 from being used). 7.5.2 data memory row address pointer (memory pointer: mp) mp is used for address modification of the data memory. the difference between ix and mp is that mp modifies the row address of an address indirectly specified by bank and operand @r. mph and ixh and mpl and ixm are assigned to the same address (addresses 7ah and 7bh of the system register) as shown in figure 7-8. actually, however, the low-order 3 bits of mph and mpl, or a total of 7 bits, function as mp. a memory pointer enable flag (mpe) which enables address modification by mp is assigned to the most significant bit of mph. when mpe = 1, the bank and row address of the data memory indirectly specified by operand @r are not bank and m r , but the address specified by mp (the column address is specified by the contents of r independently of mpe). at this time, the low-order 3 bits of mph and the most significant bit of mpl indicate bank, and the low-order 3 bits of mpl indicate a row address. remark the low-order 3 bits of mph and most significant bit of mpl of the m pd17134a subseries are fixed to 0, and bank 0 is always specified even when mpe = 1 (to prevent a bank other than 0 from being used). figure 7-8. index register configuration 00000000000 0000 7ah 7bh 7ch 7fh address initial value when reset 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 3 index register (ix) memory pointer (mp) ixh mph ixm mpl ixl bit name symbolic name flag name data 000 (mp) (ix) m p e i x e b 0 psw 0 low-order 4 bits of program status word (psword) chapter 7 system register (sysreg) 48 figure 7-9. modification of data memory address by index register and memory pointer data memory address specified by m indirect transfer address specified by @r b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 ixe mpe 00 01 10 11 bank bank m r (r) mpl (r) (r) m r bank ixh ixm setting prohibited row address bank column address b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 row address bank column address logical or mph m bank ixh ixm logical or m ixl bank m bank : bank register ix : index register ixe : index enable flag ixh : bits 10 through 8 of index register ixm : bits 7 through 4 of index register ixl : bits 3 through 0 of index register m : data memory indicated by m r and m c m r : data memory row address m c : data memory column address mp : memory pointer mpe : memory pointer enable flag mph : high-order 3 bits of memory pointer mpl : low-order 4 bits of memory pointer r : general register column address rp : general register pointer ( ) : contents addressed by : direct address such as r table 7-2. instructions subject to address modification arithmetic add r, m operation addc sub m, #n4 subc logical and operation or r, m xor m, #n4 judgment skt m, #n skf compare ske skge m, #n4 sklt skne transfer ld r, m st m, r mov m, #n4 @r, m m, @r CCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCC CCCCCCCCCCCCCCCCC chapter 7 system register (sysreg) 49 7.5.3 ixe = 0 and mpe = 0 (no data memory modification) as shown in table 7-9, data memory addresses are not affected by the index register and the data memory row address pointer. (1) data memory manipulation instructions example 1. execution of add r, m when general register is in row address 0 r003 mem 0.03h m061 mem 0.61h add r003, m061 ; addition in memories (0.03h) ? (0.03h) + (0.61h) as shown in figure 7-10, when the above instructions are executed, the data in general register address r003 and data memory address m061 are added together and the result is stored in general register address r003. (2) indirect transfer of data in the general register (horizontal indirect transfer) example 2. execution of mov @r, m when general register is in row address 0 r005 mem 0.05h m034 mem 0.34h mov r005, #8 ; r005 ? 8 (setting of column address of @r) mov @r005, m034 ; indirect transfer of data in the register (0.38h) ? (0.34h) as shown in figure 7-10, when the above instructions are executed, the data stored in data memory address m034 is transferred to data memory location 38h. the mov @r, m instruction transfers the contents of the data memory specified by m to a data memory address with the row address same as m and column address specified by @r. in the above example, therefore, data at m034 is transferred to 38h whose row address is the same as that of m034 (= 3) and column address is specified by the contents of r005 (= 8). chapter 7 system register (sysreg) 50 example 3. execution of mov m, @r when general register is in row address 0 r00b mem 0.0bh m034 mem 0.34h mov r00b, #0eh ; r00b ? 0eh (setting column address of @r) mov m034, @r00b ; indirect transfer of data in the register (0.34h) ? (0.3eh) as shown in figure 7-10, when the above instructions are executed, the contents of data memory stored at address 3eh is transferred to data memory location m034. the mov m, @r instruction transfers the contents of the data memory of the address which the column address is specified by @r to a data memory address specified by m. in the above example, therefore, data at 3eh is transferred to m034 whose row address is the same as that of m034 (= 3) and column address is specified by the contents of r00b (= 0eh). figure 7-10. operation example when ixe = 0 and mpe = 0 addresses in example 1 addresses in example 2 add r003, m061 mov @r005, m034 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address system register 8e column address specified as transfer destination column address specified as transfer source example 2. mov @r005, m034 example 3. mov m034, @r00b example 1. add r003, m061 general register 0000 bank row address column address 110 0001 0000 0011 000 0000 bank row address column address 011 0100 0000 0101 000 0000 1000 011 data memory address m general register address r indirect transfer address @r data memory address m general register address r contents of r same as m chapter 7 system register (sysreg) 51 7.5.4 ixe = 0 and mpe = 1 (diagonal indirect data transfer) as shown in figure 7-9, the indirect data transfer bank and row address specified by @r become the data memory row address pointer value only when general register indirect data transfer instructions (mov @r, m and mov m, @r) are used. example 1. execution of mov @r, m when the general register is in row address 0 r005 mem 0.05h m034 mem 0.34h mov mpl, #0110b ; mp ? 6 (setting row address of @r) mov mph, #1000b ; mpe ? 1, bank ? 0 mov r005, #8 ; r005 ? 8 (setting column address of @r) mov @r005, m034 ; indirect transfer of data in the register (0.68h) ? (0.34h) as shown in figure 7-11, when the above instructions are executed, the contents of data memory address m034 is transferred to data memory location 68h. when the mov @r, m instruction is executed when mpe = 1, the contents of the data memory address specified by m is transferred to the column address pointed to by the row address @r being pointed to by the memory pointer. in this case, the indirect address specified by @r becomes the value used for the bank and row address data memory pointer (above example uses row address 6). the column address is the value in the general register address specified by r (above example uses column address 8). therefore the address in the above example is 68h. this example is different from example 2 in 7.5.3 when mpe = 0 for the following reasons: in this example, the data memory row address pointer is used to point to the indirect address bank and row address specified by @r. (in example 2 in 7.5.3, the indirect address bank and row address are the same as m.) by setting mpe = 1, diagonal indirect data transfer can be performed using the general register. chapter 7 system register (sysreg) 52 2. execution of mov m, @r when general register is in row address 0 r00b mem 0.0bh m034 mem 0.34h mov mpl, #0110b ; mp ? 6 (setting row address of @r) mov mph, #1000b ; mpe ? 1, bank ? 0 mov r00b, #0eh ; r00b ? 0eh (setting column address of @r) mov m034, @r00b ; indirect transfer of data in the register (0.34h) ? (0.6eh) as shown in figure 7-11, when the above instructions are executed, the data stored in address 6eh is transferred to data memory location m034. figure 7-11. operation example when ixe = 0 and mpe = 1 addresses in example 1 addresses in example 2 mov @r005, m034 mov m034, @r00b 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address system register 8e column address specified as transfer destination column address specified as transfer source example 1. mov @r005, m034 general register memory pointer = 00110b example 2. mov m034, @r00b 0000 bank row address column address 011 0100 0000 1011 000 0000 1110 110 0000 bank row address column address 011 0100 0000 0101 000 0000 1000 110 data memory address m general register address r indirect transfer address @r contents of r contents of mp contents of mp contents of r data memory address m general register address r indirect transfer address @r chapter 7 system register (sysreg) 53 7.5.5 ixe = 1 and mpe = 0 (index modification) as shown in figure 7-9, when a data memory manipulation instruction is executed, any bank or address in data memory specified by m can be modified using the index register. when indirect data transfer using the general register (mov @r, m or mov m, @r) is executed, the indirect transfer bank and address specified by @r can be modified using the index register. address modification is done by performing an or operation on the data memory address and the index register. the data memory manipulation instruction being executed manipulates data in the memory location pointed to by the result of the operation (called the real address). an example is shown below. example 1. execution of add r, m when the general register is in row address 0 r003 mem 0.03h m061 mem 0.61h mov ixl, #0010b ; ix ? 00000010010b mov ixm, #0001b ; mov ixh, #0000b ; mpe ? 0 or psw, #.df.ixe and 0fh ; ixe ? 1 add r003, m061 ; (0.03h) ? (0.03h) + (0.73h) as shown in figure 7-12, when the instructions of example 1 are executed, the value in data memory address 73h (real address) and the value in general register address r003 (address 03h) are added together and the result is stored in general register address r003. when the add r, m instruction is executed, the data memory address specified by m (address 61h in above example) is index modified. modification is done by performing an or operation on data memory location m061 (address 61h, binary 00001100001b) and the index register (00000010010b in the above example). the result of the operation (00001110011b) is used as a real address (address 73h) by the instruction being executed. as compared to when ixe = 0 (examples in 7.5.3), in this example the data memory address being directly specified by m is modified by performing an or operation on m and the index register. chapter 7 system register (sysreg) 54 figure 7-12. operation example when ixe = 1 and mpe = 0 addresses in example 1 add r003, m061 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address system register general register r003 index modification example 1. add r003, m061 m061 00001100001b 00000010010b 00001110011b or) real address m061 ix : : 0000 bank row address column address 110 0001 0000 0011 000 0000 0001 110 bank 0000 0000 0011 m 001 ixm 111 0010 ixl ixh data memory address m general register address r index modification m061 ix real address (or operation) instruction is executed using this address. chapter 7 system register (sysreg) 55 example 2. indirect data transfer using the general register (execution of mov @r, m) r005 mem 0.05h m034 mem 0.34h mov ixl, #0001b ; column address ? 5 (or of 4 and 1) mov ixm, #0000b ; row address ? 3 (or of 3 and 0) mov ixh, #0000b ; mpe ? 0, bank ? 0 (or of 0 and 0) or psw, #.df.ixe and 0fh ; ixe ? 1 mov r005, #8 ; r005 ? 8 (setting column address of @r) mov @r005, m034 ; indirect data transfer using the register ; (0.38h) ? (0.35h) as shown in figure 7-13, when the above instructions are executed, the contents of data memory address 35h is transferred to data memory location 38h. when the mov @r, m instruction is executed when ixe = 1, the data memory address specified by m (direct address) is modified using the contents of the index register. the bank and row address of the indirect address specified by @r are also modified using the index register. the bank, row address, and column address specified by m (direct address) are all modified, and the bank and row address specified by @r (indirect address) are modified. therefore, in the above example the direct address is 35h and the indirect address is 38h. this example is different from example 3 in 7.5.3 when ixe = 0 for the following reasons: in this example, the bank, row address and column address of the direct address specified by m are modified using the index register. the general register is transferred to the address specified by the column address of the modified data memory address and the same row address. (in example 3 in 7.5.3, the direct address is not modified.) figure 7-13. operation example when ixe = 1 and mpe = 0 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address system register general register r005 example 2. mov @r005, m034 00000110100b 00000000001b 00000110101b 8 column address specified as transfer destination m034 direct address index modification indirect address or) real address m034 ix : : chapter 7 system register (sysreg) 56 example 3. clearing data memory of 00h-0fh to 0 m000 mem 0.00h mov ixl, #0 ; ix ? 0 mov ixm, #0 ; mov ixh, #0 ; mpe ? 0 loop: or psw, #.df.ixe and 0fh ; ixe ? 1 mov m000, #0 ; set data memory specified by ix to 0 inc ix ; ix ? ix + 1 and psw, #1110b ; ixe ? 0, remains address 7fh even if modified ; by ix because ixe is address 7fh. ske ixm, #7 ; row address 7 ? br loop ; if not 7 then loop (row address is not cleared) 4. processing an array as shown in figure 7-14, when an operation a(n) ? a(n) + 4 (0 n 15) is executed to element a (n) of a one-dimensional array with each element 8 bits long, the following instructions are executed. m000 mem 0.00h m001 mem 0.01h mov ixh, #0 mov ixm, #n shr 3 ; sets offset of row address mov ixl, #n shl 1 and 0fh ; sets offset of column address or psw, #.df.ixe and 0fh ; ixe ? 1 add m000, #4 addc m001, #0 ; a(n) ? a(n) + 4 in the above example, the value of n shifted 1 bit to the left (i.e., the value of n multiplied by 2) is set to the index register because one element is 8 bits long. figure 7-14. operation example when ixe = 1 and mpe = 0 (array processing) 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address system register a (0) a (8) a (1) a (9) a (2) a (10) a (3) a (11) a (4) a (12) a (5) a (13) a (6) a (14) a (7) a (15) b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 a (0) 00h 01h chapter 7 system register (sysreg) 57 7.6 general register pointer (rp) 7.6.1 general register pointer configuration figure 7-15 shows the configuration of the general register pointer. figure 7-15. general register pointer configuration as shown in figure 7-15, the general register pointer consists of seven bits; four bits in system register address 7dh (rph) and the high-order 3 bits of system register address 7eh (rpl). however, since the high-order 3 bits of address 7dh are always set to 0, the register effectively consists of four bits; the least significant bit of address 7dh and the high-order 3 bits of address 7eh. all register bits are cleared to 0 at reset. b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0 0 000 rpl rph 7eh 7dh address name symbol bit data initial value when reset (rp) general register pointer (rp) b c d flag chapter 7 system register (sysreg) 58 7.6.2 functions of the general register pointer the general register pointer is used to specify the location of the general register in data memory. for the general register, see chapter 8 general register (gr) . the general register consists of 16 nibbles in any single row of data memory. as shown in figure 7-16, the general register pointer is used to indicate which row address is being used as the general register. since the general register pointer effectively consists of four bits, the data memory row addresses in which the general register can be placed are address 0h to 7h of bank0 and bank1. in other words, any row in data memory can be specified as the general register. with the general register allocated in data memory, data can be transferred to and from, and arithmetic operations can be performed on the general register and data memory. note that row addressed 0h to 6h of bank1 are unmounted memory locations and should therefore not be specified as locations for the general register. for example, when instructions such as add r,m and ld r,m are executed, instruction operand r can specify an address in the general register and m specifies an address in data memory. in this way, operations like addition and data transfer can be performed on and between data memory and the general register. figure 7-16. general register configuration b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 fixed to 0 fixed to 0 fixed to 0 rph rpl general register pointer (rp) this area should not be used. allocated to the flag bcd 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 rp system register general register (16 nibbles) system register unmounted port register both banks have the same system register. example general register with rp = 0000010b area in which general register can be specified 0123456789abcdef bank1 bank0 column address chapter 7 system register (sysreg) 59 7.7 program status word (psword) 7.7.1 program status word configuration figure 7-17 shows the configuration of the program status word. figure 7-17. program status word configuration as shown in figure 7-17, the program status word consists of five bits; the least significant bit of system register address 7eh (rpl) and all four bits of system register address 7fh (psw). the program status word is divided into the following 1-bit flags: binary coded decimal flag (bcd), compare flag (cmp), carry flag (cy), zero flag (z), and the index enable flag (ixe). all register bits are cleared to 0 at reset and after the contents of the interrupt stack register have been saved. b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0 0 psw rpl 7fh 7eh address name symbol bit initial value when reset program status word (psword) i x e data (rp) b c d c m p c y z chapter 7 system register (sysreg) 60 7.7.2 functions of the program status word the flags of the program status word are used for setting conditions for arithmetic operations and data transfer instructions and for reflecting the status of operation results. figure 7-18 shows an outline of the functions of the program status word. figure 7-18. outline of functions of the program status word b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 psw rpl 7fh 7eh address symbol bit i x e flag b c d c m p c y z used to specify that index modification be performed on the data memory address used when a data memory manipulation instruction is executed. 0: index modification disabled. 1: index modification enabled. flag function ixe z cy cmp bcd set when the result of an arithmetic operation is 0. 0: indicates that the result of the arithmetic operation is a value other than 0. 1: indicates that the result of the arithmetic operation is 0. set when there is a carry in the result of an addition operation or a borrow in the result of a subtraction operation. 0: indicates there was no carry or borrow. 1: indicates there was a carry or borrow. used to specify that the result of an arithmetic operation not be stored in data memory or the general register but just be reflected in the cy and z flags. 0: results of arithmetic operations are stored. 1: results of arithmetic operations are not stored. used to specify how arithmetic operations are performed. 0: arithmetic operations are performed in 4-bit binary. 1: arithmetic operations are performed in bcd. chapter 7 system register (sysreg) 61 7.7.3 index enable flag (ixe) the ixe flag is used to specify index modification on the data memory address when a data memory manipulation instruction is executed. when the ixe flag is set to 1, an or operation is performed on the data memory address and the index register (ix), and executes an instruction to the data memory with the result of the or operation as the real address. for a more detailed explanation, see 7.5 index register (ix) and data memory row address pointer (memory pointer: mp) . 7.7.4 zero flag (z) and compare flag (cmp) the z flag indicates that the result of an arithmetic operation is 0. the cmp flag is used to specify that the result of an arithmetic operation not be stored in data memory or the general register. table 7-3 shows how the cmp flag affects the setting and resetting of the z flag. table 7-3. zero flag (z) and compare flag (cmp) conditions when cmp flag when cmp flag is 1 when the result of an arithmetic operation is a value 0 z ? 1 z flag remains unchanged when the result of an arithmetic operation is other than 0 z ? 0z ? 0 the z flag and the cmp flag are used for comparing values in the general register and data memory. the z flag is only affected by arithmetic operations. the cmp flag is only affected by bit evaluation. example of comparing 12-bit data ; are 12-bit data stored in m001, m002, and m003 equal to 456h? cmp456: set2 cmp, z sub m001, #4 ; data stored to m001, m002, and m003 are not lost sub m002, #5 sub m003, #6 ; clr1 cmp ; cmp is automatically cleared by bit judgement instruction skt1 z br differ ; 1 456 h br agree ; = 456 h 7.7.5 carry flag (cy) the cy flag shows that there is a carry in the result of an addition operation or a borrow in the result of a subtraction operation. the cy flag is set (cy = 1) when there is a carry or borrow in the result and reset (cy = 0) when there is no carry or borrow in the result. when the rorc r instruction (contents in the general register specified to by r is shifted right one bit) is executed, the following occurs: the value in the cy flag just before execution of the instruction is shifted to the most significant bit of the general register and the least significant bit is shifted to the cy flag. the cy flag is also useful for when the user wants to skip the next instruction when there is a carry or borrow in the result of an operation. the cy flag is only affected by arithmetic operations and rotations and not affected by the cmp flag. chapter 7 system register (sysreg) 62 7.7.6 binary-coded decimal flag (bcd) the bcd flag is used for bcd operations. when the bcd flag is set (bcd = 1), all arithmetic operations will be performed in bcd. when the bcd flag is reset (bcd = 0), arithmetic operations are performed in 4-bit binary. the bcd flag does not affect logical operations, bit judgement, comparison judgement or rotations. 7.7.7 notes concerning use of arithmetic operations when performing arithmetic operations (addition and subtraction) on the program status word (psword), the following point should be kept in mind. when an arithmetic operation is performed on the program status word, the result is stored in the program status word. below is an example. example mov psw, #0001b add psw, #1111b when the above instructions are executed, a carry is generated which should cause bit 2 (cy flag) of psw to be set. however, the result of the operation (0000b) is stored in psw, meaning that cy does not get set. chapter 7 system register (sysreg) 63 7.8 notes concerning use of the system register 7.8.1 reserved words for the system register because the system register is allocated in data memory, it can be used in any of the data memory manipulation instructions. as shown in example 1 (using a 17k series assembler as17k), because a data memory address can not be directly coded in an instruction operand, it needs to be defined as a symbol beforehand. the system register is data memory, but has specialized functions which make it different from general-purpose data memory. therefore, the system register is used by defining it beforehand with symbols (used as reserved words) in the assembler (as17k). reserved words for the system register are allocated in address 74h to 7fh. they are defined by the symbols (ar3, ar2, ..., psw) shown in figure 7-2. as shown in example 2, if these reserved words are used, it is not necessary to define symbols. for information concerning reserved words, see chapter 20 assembler reserved words . example 1. mov 34h, #0101b ; using a data memory address like 34h or 76h will cause an mov 76h, #1010b ; error in the assembler. m037 mem 0.37h ; addresses in general data memory need to be defined as mov m037, #0101b ; symbols using the mem directive. 2. mov ar1, #1010b ; by using the reserved word ar1 (address 6h), there is no need ; to define the address as a symbol. ; reserved word ar1 is defined in a device file with the directive ; ar1 mem 0.76h. assembler as17k has the below flag symbol manipulation instructions defined internally as macros. setn : set a flag to 1 clrn : reset a flag to 0 sktn : skip when all flags are 1 skfn : skip when all flags are 0 notn : invert a flag initflg : initialize a flag by using these embedded macro instructions, data memory can be handled as flags as shown below in example 3. the functions of the program status word and the memory pointer enable flag are defined in bit units (flag units) and each bit has a reserved word defined for it. these reserved words are mpe, bcd, cmp, cy, z and ixe. if these flag reserved words are used, the embedded macro instructions can be used as shown in example 4. chapter 7 system register (sysreg) 64 example 3. f0003 flg 0.00.3 ; flag symbol definition set1 f0003 ; embedded macro expanded macro or .mf.f0003 shr 4, #.df.f0003 and 0fh ; set bit 3 of address 00h of bank0 4. set1 bcd ; embedded macro expanded macro or .mf.bcd shr 4, #.df.bcd and 0fh ; set the bcd flag ; bcd is defined as bcd flg 0.7eh.0 clr2 z, cy ; identical address flag expanded macro and .mf.z shr 4, #.df. (not (z or cy) and 0fh) clr2 z, bcd ; different address flag expanded macro and .mf.z shr 4, #.df. (not z and 0fh) and .mf.bcd shr 4, #.df. (not bcd and 0fh) chapter 7 system register (sysreg) 65 7.8.2 handling of system register addresses fixed at 0 in dealing with system register area fixed at 0 (see figure 7-2 ), there are a few points for which caution should be taken with regard to device, emulator and assembler operation. items (1), (2) and (3) explain these points. (1) concerning device operation trying to write data to an address fixed at 0 will not change the value (0) at that address. any attempt to read an address fixed at 0 will result in the value 0 being read. (2) when using a 17k series in-circuit emulator (ie-17k or ie-17k-et) an error will be generated if a write instruction attempts to write 1 to an address fixed at 0. below is an example of the type of instructions that will cause the in-circuit emulator to generate an error. example 1. mov bank, #0100b ; attempts to write 1 to bit 3 (an address fixed at 0). 2. mov ixl, #1111b ; mov ixm, #1111b ; mov ixh, #0001b ; attempts to write 1 to bit 0 (an address fixed at 0). add ixl, #1 ; addc ixm, #0 ; addc ixh, #0 ; attempts to write 1 to bit 0 (an address fixed at 0) as a result of operation. however, when all valid bits are set to 1 as shown in example 2, executing the instructions inc ar or inc ix will not cause an error to be generated by the in-circuit emulator. this is because when all valid bits of the address register and index register are set to 1, executing the inc instruction causes all bits to be set to 0. the only time the in-circuit emulator will not generate an error when an attempt is made to write the value 1 to an address fixed at 0 is when the address being written to is in the address register. (3) when using a 17k series assembler (as17k) no error is output when an attempt is made to write 1 to an address fixed at 0. the instruction shown in example 1 mov bank, #0100b will not cause an assembler error. however, when the instruction is executed in the in-circuit emulator, an error is generated. the following is the reason why an error is not generated in the assembler: the assembler does not know what data memory address is the object of the data memory manipulation instruction being executed. the assembler generates an error only when the value n in the embedded macro bankn is a value greater than 2: this is because the assembler judges that embedded macros other than bank0 and 1 cannot be used in the m pd17134a subseries. [memo] 66 chapter 8 general register (gr) the general register (gr) is allocated in data memory. it can therefore be used directly for arithmetic operations and transferring data. 8.1 general register configuration figure 8-1 shows the configuration of the general register. as shown in figure 8-1, 16 nibbles in a single row address in data memory (16 4 bits) are used as the general register. the register pointer (rp) in the system register is used to indicate which row address is to be used as the general register. since the general register pointer effectively has four valid bits, the data memory row addresses in which the general register can be allocated are addresses 0h to 7h of bank0 and bank1. however, note that row addresses 0h to 6h of bank1 are unmounted area and should therefore not be specified as locations for the general register. 8.2 functions of the general register the general register can be used in transferring data to and from data memory and in performing arithmetic operations with data memory within an instruction. in effect, since the general register is data memory, this just means that operations such as arithmetic operations and data transfer can be performed on and between locations in data memory. in addition, because the general register is allocated in data memory, it can be controlled in the same manner as other areas in data memory through the use of data memory manipulation instructions. 67 chapter 8 general register (gr) 68 figure 8-1. general register configuration 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 address name symbol bits data reset 000 0000000 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b c d rph rpl 7dh 7eh general register pointer (rp) general register (16 nibbles) system register rp system register column address both banks have the same system register. general register when rp = 00010b the general register pointer (rp) can be used to specify any row address in address locations 0h to 7h of bank0 and bank1. however, note that row addresses 0h to 6h of bank1 are unmounted memory locations and should therefore not be specified. row address 0123456789abcdef bank0 bank1 unmounted (row addresses 0h to 6h of bank1 are unmounted memory locations. rp should therefore not specify a row address in this area). chapter 9 register file (rf) the register file is a register used mainly for specifying conditions for peripheral hardware. 9.1 register file configuration 9.1.1 configuration of the register file figure 9-1 shows the configuration of the register file. as shown in figure 9-1, the register file is a register consisting of 128 nibbles (128 words 4 bits). in the same way as with data memory, the register file is divided into addresses in 4-bit units. it has a total of 128 nibbles specified in row addresses from 0h to 7h and column addresses from 0h to 0fh. address 00h to 3fh define an area called the control register. 9.1.2 relationship between the register file and data memory figure 9-2 shows the relationship between the register file and data memory. as shown in figure 9-2, the register file overlaps with data memory in addresses 40h to 7fh. this means that the same memory exists in register file addresses 40h to 7fh and in data memory bank addresses 40h to 7fh. assuming that the current bank is bank0, register file addresses 40h to 7fh are equivalent to addresses 40h to 7fh of bank0 in data memory. when the current bank is bank1, register file addresses 40h to 7fh are equivalent to address 40h to 7fh of bank1 in data memory. figure 9-1. register file configuration 0123456789abcdef 0 1 2 3 4 5 6 7 column address row address register file control register 69 chapter 9 register file (rf) 70 9.2 functions of the register file 9.2.1 functions of the register file the register file is mainly used as a control register for specifying conditions for peripheral hardware. this control register is allocated within the register file at addresses 00h to 3fh. the rest of the register file (40h to 7fh) overlaps with data memory. as shown in 9.2.3, because of this overlap, this area of the register file is the same as normal memory with one exception: the register file manipulation instructions peek and poke can be used with this area of memory but not with normal data memory. 9.2.2 functions of control register the peripheral hardware whose conditions can be controlled by control registers is listed below. for details concerning peripheral hardware and the control register, see the section for the peripheral hardware concerned. ? stack pointer (sp) ? basic interval timer (btm) ? power-down reset ? ports ? 8-bit timer counter (tm0, tm1) ? interrupt functions ? ac zero cross detector (zcross) ? serial interface (sio) ? a/d converter figure 9-2. relationship between the register file and data memory register file column address row address 0 1 2 3 control register system register 0123456789abcdef 0 1 2 3 4 5 6 7 port register bank1 unmounted data memory bank0 port register chapter 9 register file (rf) 71 9.2.3 register file manipulation instructions reading and writing data from and to the register file is done using the window register (wr: address 78h) located in the system register. reading and writing of data is performed using the following dedicated instructions: peek wr, rf: read the data in the address specified by rf and put it into wr. poke rf, wr: write the data in wr into the address specified by rf. below is an example using the peek and poke instructions. example rf02 mem0.82h ; symbol definition rf1f mem0.9fh ; register file addresses 00h to 3fh must be defined with rf53 mem0.53h ; symbols as bank0 addresses 80h to bfh. rf6d mem0.6dh ; see 9.4 notes concerning use of the register file rf70 mem1.70h ; for details. rf71 mem1.71h ; bank0 1 peek wr, rf02 ; 2 poke rf1f, wr ; 3 peek wr, rf53 ; 4 poke rf6d, wr ; bank1 ; 5 peek wr, rf02 ; 6 poke rf1f, wr ; 7 peek wr, rf70 ; 8 poke rf72, wr ; figure 9-3 shows an example of register file operation. as shown in figure 9-3, reading and writing of data to and from the control register (addresses 00h to 3fh) is performed using the peek wr, rf and poke rf, wr instructions. data within the control register specified using rf can be read from and written to the control register, only by using these instructions with the window register. the fact that the register file overlaps with data memory in addresses 40h to 7fh has the following effect: when a peek wr, rf or poke rf, wr instruction is executed, the effect is the same as if they were being executed on the data memory address (in the current bank) specified by rf. addresses 40h to 7fh of the register file can be operated by normal memory manipulation instructions. chapter 9 register file (rf) 72 figure 9-3. accessing the register file using the peek and poke instructions 9.3 control register figure 9-4 shows the configuration of the control register. as shown in figure 9-4, the control register consists of 64 nibbles (64 5 4 bits) allocated in register file addresses 00h to 3fh. however, only 26 nibbles are actually used. the remaining 38 nibbles are allocated for registers which have not yet been implemented. data should not be read from or written to this area. there are two types of registers, both of which occupy one nibble of memory. one type is read/write (r/w), and the other is read-only (r). note that within the read/write (r/w) flags, there exists a flag that will always be read as 0. the following read/write (r/w) flags are those flags which will always be read as 0: wr 0123456789abcdef 0 1 2 3 4 5 6 7 0 3 1 2 3 4 5 6 7 bank0 3 peek wr, rf53 8 poke rf72, wr 7 peek wr, rf70 4 poke rf6d, wr bank1 unmounted system register 1 poke rf1f, wr control register register file for bank0 register file for bank1 row address column address data memory 5 2 6 peek wr, rf02 chapter 9 register file (rf) 73 ? wdtres (rf: 03h, bit 3) ? wdten (rf: 03h, bit 0) ? tm0res (rf: 11h, bit 2) ? tm1res (rf: 12h, bit 2) ? btmres (re: 13h, bit 2) ? adcstrt (rf: 20h, bit 0) within the four bits of data in a nibble, there are bits which are fixed at 0 and will therefore always be read as 0. these bits remain fixed at 0 even when an attempt is made to write to them. attempting to read data in the unused register address area (38 nibbles) will yield unpredictable values. in addition, attempting to write to this area has no effect. 9.4 notes concerning use of the register file 9.4.1 notes concerning operation of the control register (read-only and unused registers) it is necessary to take note of the following notes concerning device operation and use of the 17k series assembler (as17k) and in-circuit emulator (ie-17k or ie-17k-et) with regard to the read-only (r) and unused registers in the control register (register file addresses 00h to 3fh). (1) device operation writing to a read-only register has no effect. attempting to read data from an address in the unused data area will yield an undefined value. attempting to write to an address in the unused data area has no effect. (2) during use of the assembler (as17k) an error will be generated if an attempt is made to write to a read-only register. an error will also be generated if an attempt is made to read from or write to an address in the unused data area. (3) during use of the in-circuit emulator (ie-17k or ie-17k-et) (operation during patch processing and similar operations) attempting to write to a read-only register has no effect. no error is generated. attempting to read data from an address in the unused data area will yield an undefined value. attempting to write to an address in the unused data area has no effect. no errors are generated. 9.4.2 register file symbol definitions and reserved words attempting to use a numerical value in a 17k series assembler (as17k) to specify a register file address in the rf operand of the peek wr, rf or poke rf, wr instructions will cause an error to be generated. therefore, as shown in example 1, register file addresses need to be defined beforehand as symbols. example 1. case which causes an error to be generated peek wr, 02h ; poke 21h, wr ; case in which no error is generated rf71 mem0.71h ; symbol definition peek wr, rf71 ; chapter 9 register file (rf) 74 caution should especially be taken with regard to the following point: ? when using a symbol to define the control register as an address in data memory, it needs to be defined as addresses 80h to bfh of bank0. since the control register is manipulated using the window register, any attempt to manipulate the control register other than by using the peek and poke instructions needs to cause an error in the assembler. however, note that any address in the area of the register file overlapping with data memory (addresses 40h to 7fh) can be defined as a symbol in the same manner as with normal data memory. an example is given below. example 2. rf71 mem 1.71h ; register file overlapping with data memory rf02 mem 0.82h ; control register bank0 peek wr, rf71 ; rf71 becomes address 71h in bank0. peek wr, rf02 ; rf02 becomes address 02h in the control register. bank1 peek wr, rf71 ; rf71 becomes address 71h in bank1. peek wr, rf02 ; rf02 becomes address 02h in the control register. the assembler (as17k) has the below flag symbol manipulation instructions defined internally as macros. setn : set a flag to 1 clrn : reset a flag to 0 sktn : skip when all flags are 1 skfn : skip when all flags are 0 notn : invert a flag initflg : initialize a flag by using these embedded macro instructions, the contents of the register file can be manipulated in 1-bit unit. due to the fact that most of control register consists of 1-bit flags, the assembler (as17k) has reserved words for use with these flags. however, note that there is no reserved word for the stack pointer for its use as a flag. the only reserved word used for the stack pointer is the reserved word sp, for its use as data memory. for this reason, none of the above flag manipulation instructions can be used with the stack pointer. chapter 9 register file (rf) 75 figure 9-4. control register configuration (1/2) remark the address in parentheses apply when the as17k assembler is used. the names of all the flags in the control registers are assembler reserved words saved in the device file. using these reserved words is useful in programming. (see chapter 20 assembler reserved words .) 01234567 column address row address item symbol when reset read/ write symbol when reset read/ write symbol when reset read/ write symbol when reset read/ write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r p d r e s e n 000 0000000010000000 000000000000 010100000000 t m 0 e n t m 0 r e s t m 0 c k 0 t m 1 e n t m 1 r e s t m 1 c k 0 b t m i s e l b t m r e s b t m c k 1 b t m c k 0 t m 1 c k 1 t m 0 c k 1 a d c s t r t 000 a d c s o f t a d c c m p 0 a d c e n d a d c c h 3 a d c c h 2 a d c c h 1 a d c c h 0 s p s i o t s s i o h i z s i o c k 1 s i o c k 0 000 w d t r e s w d t e n 0 (8) 1 (9) 2 (a) 3 (b) chapter 9 register file (rf) 76 figure 9-4. control register configuration (2/2) note the value of the int flag changes every moment according to the status of the int pin. 8 9 abcdef r/w r/w r/w r/w p 0 c 0 i d i 000000000000 p 0 c b i o 0 z c r o s s r/w r/w 000000000001 i r q s i o r/w r/w s i o e n 00000000 000 note p 0 b g p u r/w r/w r/w r/w p 0 d b i o 0 00000000 00000000 0 i p s i o r t m 0 o s e l p 0 a g p u i n t 0000 i e g m d 0 i e g m d 1 0 0 0 p 0 c 1 i d i p 0 c b i o 1 p 0 c 2 i d i p 0 c b i o 2 p 0 c 3 i d i p 0 c b i o 3 00 i p b t m i p t m 1 i p t m 0 i p r/w r/w r/w 0 0 0 p 0 d b i o 1 p 0 d b i o 2 p 0 d b i o 3 p 0 a g i o p 0 b g i o p 1 a g i o 0 0 0 i r q b t m 0 0 0 i r q t m 1 0 0 0 0000 i r q t m 0 0 0 0 0000 i r q 0 0 0 0 0 0 00 00 chapter 10 data buffer (dbf) the data buffer consists of four nibbles allocated in addresses 0ch to 0fh in bank0. the data buffer acts as a data storage area for the cpu peripheral circuit (address register, serial interface, timer 0, timer1, basic internal timer, and a/d converter) through use of the get and put instructions. it also acts as data storage used for receiving and transferring data. by using the movt, dbf, and @ar instructions, fixed data in program memory can be read into the data buffer. 10.1 data buffer configuration figure 10-1 shows the allocation of the data buffer in data memory. as shown in figure 10-1, the data buffer is allocated in address locations 0ch to 0fh in bank0 and consists of a total of 16 bits (4 4 bits). figure 10-1. allocation of the data buffer figure 10-2 shows the configuration of the data buffer. as shown in figure 10-2, the data buffer is made up of 16 bits with its lsb in bit 0 of address 0fh and its msb in bit 3 of address 0ch. figure 10-2. data buffer configuration because the data buffer is allocated in data memory, it can be used in any of the data memory manipulation instructions. 0123456789abc data buffer (dbf) ef 0 1 2 3 4 5 6 7 column address data memory system register (sysreg) row address d bank0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0dh 0ch address data data buffer b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 0fh 0eh b 11 b 10 b 9 b 8 b 15 b 14 b 13 b 12 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 data memory bank0 bit bit symbol data m s b l s b ^ ^ ^ ^ dbf3 dbf2 dbf1 dbf0 77 chapter 10 data buffer (dbf) 78 10.2 functions of the data buffer the data buffer has two separate functions. the data buffer is used for data transfer with peripheral hardware. the data buffer is also used for reading constant data (table reference) in program memory. figure 10-3 shows the relationship between the data buffer and peripheral hardware. figure 10-3. relationship between the data buffer and peripheral hardware data buffer (dbf) internal bus constant data program memory (rom) peripheral address 01h 02h 03h 04h peripheral hardware shift register (siosfr) timer 0 modulo register (tm0m) timer 1 modulo register (tm1m) address register (ar) 40h a/d converter data register (adcr) 45h timer 0/timer 1 count register (tm0tm1c) chapter 10 data buffer (dbf) 79 10.2.1 data buffer and peripheral hardware table 10-1 shows data transfer with peripheral hardware using the data buffer. each unit of peripheral hardware has an individual address (called its peripheral address). by using this peripheral address and the dedicated instructions get and put, data can be transferred between each unit of peripheral hardware and the data buffer. get dbf, p: read the data in the peripheral hardware address specified by p into the data buffer (dbf). put p, dbf: write the data in the data buffer to the peripheral hardware address specified by p. there are three types of peripheral hardware units: read/write (put/get), write-only (put) and read-only (get). the following describes what happens when a get instruction is used with write-only hardware (put only) and when a put instruction is used with read-only hardware (get only). ? reading (get) from write-only (put only) peripheral hardware will yield an undefined value. ? writing (put) to read-only (get only) peripheral hardware has no effect (same as a nop instruction). table 10-1. peripheral hardware (1) peripheral hardware with input/output in 8-bit units peripheral name peripheral hardware direction of data actual address put get bit length 01h siosfr serial interface 8 bits 02h tm0m timer 0 8 bits 03h tm1m timer 1 8 bits 04h adcr a/d converter 8 bits (2) peripheral hardware with input/output in 16-bit units peripheral name peripheral hardware direction of data actual address put get bit length 40h ar address register 10/11 bits note 45h tm0tm1c timer 0/timer 1 count register 16 bits note 10 bits for the m pd17134a and 17135a, and 11 bits for the m pd17136a and 17137a. chapter 10 data buffer (dbf) 80 10.2.2 data transfer with peripheral hardware data can be transferred between the data buffer and peripheral hardware in 8- or 16-bit units. instruction execution time for a single put or get instruction is the same regardless of whether 8 or 16 bits are being transferred. example 1. put instruction (when the actual bits in peripheral hardware are the 8 bits from 0 to 7) when only 8 bits of data are being written from the data buffer, the high-order 8 bits (dbf3, dbf2) are dont care (any value can be written). 2. get instruction (when the actual bits in peripheral hardware are the 8 bits from 0 to 7) when 8 bits of data are being read into the data buffer, the values in the high-order 8 bits (dbf3, dbf2) remain unchanged. b 3 b 2 b 1 b 0 b 6 b 5 b 4 b 7 dbf3 dbf2 dbf1 dbf0 don't care don't care b 0 b 7 actual bits data in peripheral hardware put data buffer b 0 b 7 dbf3 dbf2 dbf1 dbf0 retained retained b 0 b 7 actual bits data in peripheral hardware get data buffer chapter 10 data buffer (dbf) 81 10.2.3 table reference by using the movt instruction, constant data in program memory (rom) can be read into the data buffer. the movt instruction is explained below. movt dbf, @ar: the contents of the program memory being specified by the address register (ar) is read into the data buffer (dbf). dbf3 dbf2 dbf1 dbf0 16 bits movt dbf, @ar data buffer b 15 program memory (rom) b 0 [memo] 82 chapter 11 arithmetic and logic unit (alu) the alu is used for performing arithmetic operations, logical operations, bit judgements, comparison judgements, and rotations on 4-bit data. 11.1 alu block configuration figure 11-1 shows the configuration of the alu block. as shown in figure 11-1, the alu block consists of the main 4-bit data processor, temporary registers a and b which are peripheral circuit of the alu, the status flip-flop for controlling the status of the alu, and the decimal correction circuit for use during arithmetic operations in bcd. as shown in figure 11-1, the status flip-flop consists of the following flags: zero flag ff, carry flag ff, compare flag ff, and the bcd flag ff. each flag in the status flip-flop corresponds directly to a flag in the program status word (psword: addresses 7eh, 7fh) in the system register. the flags in the program status word are the following: zero flag (z), carry flag (cy), compare flag (cmp), and the bcd flag (bcd). 11.2 functions of the alu block arithmetic operations, logical operations, bit judgements, comparison judgements, and rotations are performed using the instructions in the alu block. table 11-1 lists each arithmetic/logical instruction, judgement instruction, and rotation instruction. by using the instructions listed in table 11-1, 4-bit arithmetic/logical operations, judgements and rotations can be performed in a single instruction. arithmetic operations in decimal can also be performed in a single instruction. 11.2.1 functions of the alu the arithmetic operations consist of addition and subtraction. arithmetic operations can be performed on the contents of the general register and data memory or on immediate data and the contents of data memory. operations in binary are performed on 4 bits of data and operations in decimal are performed on one place (bcd operation). logical operations include anding, oring, and xoring. their operands can be general register contents and data memory contents, or data memory contents and immediate data. bit judgement is used to determine whether bits in 4-bit data in data memory are 0 or 1. comparison judgement is used to compare contents of data memory with immediate data. it is used to determine whether one value is equal to or greater than the other, less than the other, or if both values are equal or not equal. rotation is used to shift 4-bit data in the general register one bit in the direction of its least significant bit (rotation to the right). 83 chapter 11 arithmetic and logic unit (alu) 84 figure 11-1. alu configuration data bus temporary register a temporary register b status flip-flop alu arithmetic operations logical operations bit judgement comparison judgement rotations decimal correction circuit 7eh b 0 bcd b 3 b 2 b 1 b 0 cmp cy z ixe 7fh program status word (psword) address name bit flag status flip-flop bcd flag ff cmp flag ff cy flag ff z flag ff function outline indicates when the result of an arithmetic operation is 0. stores the borrow or carry from an arithmetic operation. used to indicate whether to store the result of an arithmetic operation. used to indicate whether to perform decimal correction for arithmetic operations. chapter 11 arithmetic and logic unit (alu) 85 [memo] chapter 11 arithmetic and logic unit (alu) 86 table 11-1. list of alu instructions (1/2) alu function instruction operation explanation arithmetic addition add r, m (r) ? (r) + (m) adds contents of general register and data memory. operations result is stored in general register. add m, #n4 (m) ? (m) + n4 adds immediate data to contents of data memory. result is stored in data memory. addc r, m (r) ? (r) + (m) + cy adds contents of general register, data memory and carry flag. result is stored in general register. addc m, (m) ? (m) + n4 + cy adds immediate data, contents of data memory and carry #n4 flag. result is stored in data memory. subtraction sub r, m (r) ? (r) C (m) subtracts contents of data memory from contents of general register. result is stored in general register. sub m, #n4 (m) ? (m) C n4 subtracts immediate data from data memory. result is stored in data memory. subc r, m (r) ? (r) C (m) C cy subtracts contents of data memory and carry flag from contents of general register. result is stored in general register. subc m, (m) ? (m) C n4 C cy subtracts immediate data and carry flag from data memory. #n4 result is stored in data memory. logical logical or r, m (r) ? (r) v (m) or operation is performed on contents of general register operations or and data memory. result is stored in general register. or m, #n4 (m) ? (m) v n4 or operation is performed on immediate data and contents of data memory. result is stored in data memory. logical and r, m (r) ? (r) (m) and operation is performed on contents of general register and and data memory. result is stored in general register. and m, #n4 (m) ? (m) n4 and operation is performed on immediate data and contents of data memory. result is stored in data memory. logical xor r, m (r) ? (r) v (m) xor operation is performed on contents of general register xor and data memory. result is stored in general register. xor m, #n4 (m) ? (m) v n4 xor operation is performed on immediate data and contents of data memory. result is stored in data memory. bit true skt m, #n cmp ? 0, if (m) n=n, skips next instruction if all bits in data memory specified by judgement then skip n are true (1). result is not stored. false skf m, #n cmp ? 0, if (m) n=0, skips next instruction if all bits in data memory specified by then skip n are false (0). result is not stored. comparison equal ske m, #n4 (m) C n4, skip if zero skips next instruction if immediate data equals contents of judgement data memory. result is not stored. not equal skne m, (m) C n4, skip if not skips next instruction if immediate data is not equal to #n4 zero contents of data memory. result is not stored. 3 skge m, (m) C n4, skip if not skips next instruction if contents of data memory is greater #n4 borrow than or equal to immediate data. result is not stored. < sklt m, (m) C n4, skip if skips next instruction if contents of data memory is less #n4 borrow than immediate data. result is not stored. rotation rotate to rorc r rotate contents of the general register along with the cy the right flag to the right. result is stored in general register. v v cy ? (r) b3 ? (r) b2 ? (r) b1 ? (r) b0 v v chapter 11 arithmetic and logic unit (alu) 87 table 11-1. list of alu instructions (2/2) alu function difference in operation because of program status word (psword) arithmetic operation logical operation bit judgement comparison rotation dontcare dont care not affected dont care dont care executed (retained) (retained) (retained) (retained) dontcare reset not affected dont care dont care executed (retained) (retained) (retained) dontcare dont care not affected dont care dont care executed (retained) (retained) (retained) (retained) dontcare dont care not affected value of b 0 of dont care executed (retained) (retained) general register (retained) value of value of operation cy flag z flag modification bcd flag cmp flag when ixe = 1 0 0 binary operation. set if operation result is 0000b; executed result is stored. otherwise, reset 0 1 binary operation. retains status if operation result result is not stored. is 0000b; otherwise, reset 1 0 bcd operation. set if operation result is 0000b; result is stored. otherwise, reset 1 1 bcd operation. retains status if operation result result is not stored. is 0000b; otherwise, reset set when carry or borrow occurs; otherwise, reset CCC CCCCCCCCCCCC CCC CCCCCCCCCCCC CCC CCCCCCCCCCCC CCC CCCCCCCCCCCC CCC CCCCCCCCCCCC CCC CCCCCCCCCCCC CCC CCCCCCCCCCCC CCC CCCCCCCCCCCC C CCC CCCCCCCCC CCC CCCCCCCCCCCC C CCC CCCCCCCCC CCC CCCCCCCCCCCC C CCC CCCCCCCCC CCC CCCCCCCCCCCC C CCC CCCCCCCCC CCC CCCCCCCCCCCC C CCC CCCCCCCCC CCC CCCCCCCCCCCC C CCC CCCCCCCCC CCC CCCCCCCCCCCC C CCC CCCCCCCCC CCC CCCCCCCCCCC CCC CCC CCCCCCCCCCC CCC CCC CCCCCCCCCCC CCC CCC CCCCCCCCCCC CCC CCC CCCCCCCCCCC CCC CCC CCCCCCCCCCC CCC CCC CCCCCCCCCCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC CCC chapter 11 arithmetic and logic unit (alu) 88 11.2.2 functions of temporary registers a and b temporary registers a and b are needed for processing of 4-bit data at a time. these registers are used for temporary storage of the first and second data operands of an instruction. 11.2.3 functions of the status flip-flop the status flip-flop is used for controlling operation of the alu and for storing data which has been processed. each flag in the status flip-flop corresponds directly to a flag in the program status word (psword) located in the system register. this means that when a flag in the system register is manipulated it is the same as manipulating a flag in the status flip-flop. each flag in the program status word is described below. (1) z flag this flag is set (1) when the result of an arithmetic operation is 0000b, otherwise it is reset (0). however, depending on the status of the cmp flag, the conditions which cause this flag to be set (1) can be changed. (i) when cmp = 0 z flag is set (1) when the result of an arithmetic operation is 0000b, otherwise it is reset (0). (ii) when cmp = 1 the previous state is maintained when the result of an arithmetic operation is 0000b, otherwise it is reset (0). only affected by arithmetic operations. (2) cy flag this flag is set (1) when a carry or borrow is generated as a result of an arithmetic operation, otherwise it is reset (0). when an arithmetic operation is being performed using a carry or borrow, the operation is performed using the cy flag as the least significant bit. when a rotation (rorc instruction) is performed, the contents of the cy flag becomes the most significant bit (b 3 ) of the general register and the least significant bit of the general register is stored in the cy flag. only affected by arithmetic operations and rotations. (3) cmp flag when the cmp flag is set (1), the result of an arithmetic operation is not stored in either the general register or data memory. when the bit evaluation instruction is performed, the cmp flag is reset (0). the cmp flag does not affect comparison judgements, logical operations, or rotations. (4) bcd flag when the bcd flag is set (1), decimal correction is performed for all arithmetic operations. when the flag is reset (0), 4-bit binary operation is performed. the bcd flag does not affect logical operations, bit judgements, comparison judgements, or rotations. these flags can also be set through direct manipulation of the values in the program status word. at this time, the corresponding flag in the status flip-flop is also manipulated. chapter 11 arithmetic and logic unit (alu) 89 addition in bcd operation result operation result operation result operation result operation subtraction in 4-bit binary subtraction in bcd 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1110 1111 1100 1101 1110 1111 1100 1101 1010 1011 1100 1101 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1100 1101 1110 1111 1100 1101 1110 1111 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 cy cy cy cy addition in 4- bit binary operation result 11.2.4 operations in 4-bit binary when the bcd flag is set to 0, arithmetic operations are performed in 4-bit binary. 11.2.5 operations in bcd when the bcd flag is set to 1, decimal correction is performed for arithmetic operations performed in 4-bit binary. table 11-2 shows the differences in the results of operations performed in 4-bit binary and in bcd. when the result of an addition after decimal correction is equal to or greater than 20, or the result of a subtraction after decimal correction is outside of the range C10 to +9, a value of 1010b (0ah) or higher is stored as the result (shaded area in table 11-2). table 11-2. results of arithmetic operations performed in 4-bit binary and bcd chapter 11 arithmetic and logic unit (alu) 90 11.2.6 operations in the alu block when arithmetic operations, logical operations, bit judgements, comparison judgements or rotations in a program are executed, the first data operand is stored in temporary register a and the second data operand is stored in temporary register b. the first data operand is 4-bit data used to specify the contents of an address in the general register or data memory. the second data operand is 4-bit data used to either specify the contents of an address in data memory or to be used as an immediate value. for example, in the instruction add r, m second operand first operand the first operand, r, is used to specify the contents of an address in the general register. the second operand, m, is used to specify the contents of an address in data memory. in the instruction add m, #n4 the first operand, m, is used to specify an address in data memory. the second operand, #n4, is immediate data. in the rotation instruction rorc r only the first operand, r (used to specify the contents of an address in the general register) is used. next, using the data stored in temporary registers a and b, the alu executes the operation specified by the instruction (arithmetic operation, logical operation, bit judgement, comparison judgement, or rotation). when the instruction being executed is an arithmetic operation, logical operation, or rotation, the data processed by the alu is stored in the location specified by the first operand (general register address or data memory address) and the operation terminates. when the instruction being executed is a bit judgement or comparison judgement, the result processed by the alu is used to determine whether or not to skip the next instruction (whether to treat next instruction as a nop instruction) and the operation terminates. caution should be taken with regard to the following points: (1) arithmetic operations are affected by the cmp and bcd flags in the program status word. (2) logical operations are not affected by the cmp or bcd flag in the program status word. logical operations do not affect the z or cy flags. (3) bit judgement causes the cmp flag in the program status word to be reset. (4) when an arithmetic operation, logical operation, bit judgement, comparison judgement, or rotation is being executed and the ixe flag in the program status word is set (1), address modification is performed using the index register. chapter 11 arithmetic and logic unit (alu) 91 11.3 arithmetic operations (addition and subtraction in 4-bit binary and bcd) as shown in table 11-3, arithmetic operations consist of addition, subtraction, addition with carry, and subtraction with borrow. these instructions are add, addc, sub, and subc. the add, addc, sub, and subc instructions are further divided into addition and subtraction of the general register and data memory and addition and subtraction of data memory and immediate data. when the operands r and m are used, addition or subtraction is performed using the general register and data memory. when the operands m and #n4 are used, addition or subtraction is performed using data memory and immediate data. arithmetic operations are affected by the status flip-flop and the program status word (psword) in the system register. the bcd flag in the program status word is used to specify whether arithmetic operations are to be performed in 4-bit binary or in bcd. the cmp flag is used to specify whether or not the results of arithmetic operations are to be stored. 11.3.1 to 11.3.4 explain the relationship between each command and the program status word. table 11-3. types of arithmetic operations 11.3.1 addition and subtraction when cmp = 0 and bcd = 0 addition and subtraction are performed in 4-bit binary and the result is stored in the general register or data memory. when the result of the operation is greater than 1111b (carry generated) or less than 0000b (borrow generated), the cy flag is set (1); otherwise it is reset (0). when the result of the operation is 0000b, the z flag is set (1) regardless of whether there is carry or borrow; otherwise it is reset (0). 11.3.2 addition and subtraction when cmp = 1 and bcd = 0 addition and subtraction are performed in 4-bit binary. however, because the cmp flag is set (1), the result of the operation is not stored in either the general register or data memory. when there is a carry or borrow in the result of the operation, the cy flag is set (1); otherwise it is reset (0). when the result of the operation is 0000b, the previous state of the z flag is retained; otherwise it is reset (0). general register and data memory add r, m data memory and immediate data add m, #n4 general register and data memory addc r, m data memory and immediate data addc m, #n4 general register and data memory sub r, m data memory and immediate data sub m, #n4 general register and data memory subc r, m data memory and immediate data subc m, #n4 without carry add with carry addc without borrow sub with borrow subc addition subtraction arithmetic operation chapter 11 arithmetic and logic unit (alu) 92 11.3.3 addition and subtraction when cmp = 0 and bcd = 1 bcd operations are performed. the result of the operation is stored in the general register or data memory. when the result of the operation is greater than 1001b (9d) or less than 0000b (0d), the carry flag is set (1), otherwise it is reset (0). when the result of the operation is 0000b (0d), the z flag is set (1), otherwise it is reset (0). operations in bcd are performed by first computing the result in binary and then by using the decimal correction circuit to convert the result to decimal. for information concerning the binary to decimal conversion, see table 11-2 . in order for operations in bcd to be performed properly, note the following: (1) result of an addition must be in the range 0d to 19d. (2) result of a subtraction must be in the range 0d to 9d, or in the range C10d to C1d. the following shows which value is considered the cy flag in the range 0d to 19d (shown in 4-bit binary): 0, 0000b to 1, 0011b cy cy the following shows which value is considered the cy flag in the range C10d to C1d (shown in 4-bit binary): 1, 0110b to 1, 1111b cy cy when operations in bcd are performed outside of the limits of (1) and (2) stated above, the cy flag is set (1) and the result of operation is output as a value greater than or equal to 1010b (0ah). 11.3.4 addition and subtraction when cmp = 1 and bcd = 1 bcd operations are performed. the result is not stored in either the general register or data memory. in other words, the operations specified by cmp = 1 and bcd = 1 are both performed at the same time. example mov rpl, #0001b ; sets the bcd flag (bcd = 1). mov psw, #1010b ; sets the cmp and z flag (cmp = 1, z = 1) and resets the cy flag ; (cy = 0). sub m1, #0001b ; (1) subc m2, #0010b ; (2) subc m3, #0011b ; (3) by executing the instructions in steps numbered (1), (2), and (3), the 12 bits in memory locations m1, m2, and m3 and the immediate data (321) can be compared in decimal. 11.3.5 notes concerning use of arithmetic operations when performing arithmetic operations with the program status word (psword), caution should be taken with regard to the result of the operation being stored in the program status word. normally, the cy and z flags in the program status word are set (1) or reset (0) according to the result of the arithmetic operation being executed. however, when an arithmetic operation is performed on the program status word itself, the result is stored in the program status word. this means that there is no way to determine if there is a carry or borrow in the result of the operation nor if the result of the operation is zero. however, when the cmp flag is set (1), results of arithmetic operations are not stored. therefore, even in the above case, the cy and z flags will be properly set (1) or reset (0) according to the result of the operation. chapter 11 arithmetic and logic unit (alu) 93 11.4 logical operations as shown in table 11-4, logical operations consist of logical or, logical and, and logical xor. accordingly, the logical operation instructions are or, and, and xor. the or, and, and xor instructions can be performed on either the general register and data memory, or on data memory and immediate data. the operands of these instructions are specified in the same way as for arithmetic operations (r, m or m, #n4). logical operations are not affected by the bcd or cmp flags in the program status word (psword). logical operations do not cause either the cy or z flag in the program status word (psword) to be set. however, when the index enable flag (ixe) is set (1), index modification is performed using the index register. table 11-4. logical operations table 11-5. table of true values for logical operations logical and c = a and b a 0 0 1 1 logical or c = a or b logical xor c = a xor b a 0 0 1 1 b 0 1 0 1 c 0 0 0 1 b 0 1 0 1 c 0 1 1 1 a 0 0 1 1 b 0 1 0 1 c 0 1 1 0 general register and data memory or r, m data memory and immediate data or m, #n4 general register and data memory and r, m data memory and immediate data and m, #n4 general register and data memory xor r, m data memory and immediate data xor m, #n4 logical operation logical or logical and logical xor chapter 11 arithmetic and logic unit (alu) 94 11.5 bit judgements as shown in table 11-6, there are both true (1) and false (0) bit judgement instructions. the true (1) and false (0) bit judgements use skt and skf instruction, respectively the skt and skf instructions can only be used with data memory. bit judgements are not affected by the bcd flag in the program status word (psword) and bit judgements do not cause either the cy or z flag in the program status word (psword) to be set. however, when an skt or skf instruction is executed, the cmp flag is reset (0). when the index enable flag (ixe) is set (1), index modification is performed using the index register. for information concerning index modification using the index register, see chapter 7 system register (sysreg) . 11.5.1 and 11.5.2 explain true (1) and false (0) bit judgements. table 11-6. bit judgement instructions 11.5.1 true (1) bit judgement the true (1) bit judgement instruction (skt m, #n) is used to determine whether or not the bits specified by n in the 4 bits of data memory m are true (1). when all bits specified by n are true (1), this instruction causes the next instruction to be skipped. example mov m1, #1011b skt m1, #1011b ; (1) br a br b skt m1, #1101b ; (2) br c br d in this example, bits 3, 1, and 0 of data memory m1 are judged in step number (1). because all the bits are true (1), the program branches to b. in step number (2), bits 3, 2, and 0 of data memory m1 are judged. since bit 2 of data memory m1 is false (0), the program branches to c. true (1) bit judgement skt m, #n false (0) bit judgement skf m, #n bit judgement chapter 11 arithmetic and logic unit (alu) 95 11.5.2 false (0) bit judgement the false (0) bit judgement instruction (skf m, #n) is used to determine whether or not the bits specified by n in the 4 bits of data memory m are false (0). when all bits specified by n are false (0), this instruction causes the next instruction to be skipped. example mov m1, #1001b ; skf m1, #0110b ; (1) br a ; br b ; skf m1, #1110b ; (2) br c ; br d ; in this example, bits 2 and 1 of data memory m1 are judged in step number (1). because both bits are false (0), the program branches to b. in step number (2), bits 3, 2, and 1 of data memory m1 are judged. since bit 3 of data memory m1 is true (1), the program branches to c. chapter 11 arithmetic and logic unit (alu) 96 11.6 comparison judgements as shown in table 11-7, there are comparison judgement instructions for determining if one value is equal to, not equal to, greater than or equal to, or less than another. the ske instruction is used to determine if two values are equal. the skne instruction is used to determine two values are not equal. the skge instruction is used to determine if one value is greater than or equal to another and the sklt instruction is used to determine if one value is less than another. the ske, skne, skge, and sklt instructions perform comparisons between a value in data memory and immediate data. in order to compare values in the general register and data memory, a subtraction instruction is performed according to the values in the cmp and z flags in the program status word (psword). for more information concerning comparison of the general register and data memory, see 11.3 arithmetic operations . comparison judgements are not affected by the bcd or cmp flags in the program status word (psword) and comparison judgements do not cause either the cy or z flags in the program status word (psword) to be set. 11.6.1 to 11.6.4 explain the equal to, not equal to, greater than or equal to, and less than comparison evaluations. table 11-7. comparison judgement instructions 11.6.1 equal to judgement the "equal to" judgement instruction (ske m, #n4) is used to determine if immediate data and the contents of a location in data memory are equal. this instruction causes the next instruction to be skipped when the immediate data and the contents of data memory are equal. example mov m1, #1010b ske m1, #1010b ; (1) br a br b ; ske m1, #1000b ; (2) br c br d in this example, because the contents of data memory m1 and immediate data 1010b in step number (1) are equal, the program branches to b. in step number (2), because the contents of data memory m1 and immediate data 1000b are not equal, the program branches to c. equal to ske m, #n4 not equal to skne m, #n4 greater than or equal to skge m, #n4 less than sklt m, #n4 comparison judgement chapter 11 arithmetic and logic unit (alu) 97 11.6.2 not equal to judgement the not equal to judgement instruction (skne m, #n4) is used to determine if immediate data and the contents of a location in data memory are not equal. this instruction causes the next instruction to be skipped when the immediate data and the contents of data memory are not equal. example mov m1, #1010b skne m1, #1000b ; (1) br a br b ; skne m1, #1010b ; (2) br c br d in this example, because the contents of data memory m1 and immediate data 1000b in step number (1) are not equal, the program branches to b. in step number (2), because the contents of data memory m1 and immediate data 1010b are equal, the program branches to c. 11.6.3 greater than or equal to judgement the greater than or equal to judgement instruction (skge m, #n4) is used to determine if the contents of a location in data memory is a value greater than or equal to the value of the immediate data operand. if the value in data memory is greater than or equal to that of the immediate data, this instruction causes the next instruction to be skipped. example mov m1, #1000b skge m1, #0111b ; (1) br a br b ; skge m1, #1000b ; (2) br c br d ; skge m1, #1001b ; (3) br e br f in this example, the program will first branch to b since the value in data memory is larger than that of the immediate data. next it will branch to d since the value in data memory is equal to that of the immediate data. last it will branch to e since the value in data memory is less than that of the immediate data. chapter 11 arithmetic and logic unit (alu) 98 11.6.4 less than judgement the less than judement instruction (sklt m, #n4) is used to determine if the contents of a location in data memory is a value less than that of the immediate data operand. if the value in data memory is less than that of the immediate data, this instruction causes the next instruction to be skipped. example mov m1, #1000b sklt m1, #1001b ; (1) br a br b ; sklt m1, #1000b ; (2) br c br d ; sklt m1, #0111b ; (3) br e br f in this example, the program will first branch to b since the value in data memory is less than that of the immediate data. next it will branch to c since the value in data memory is equal to that of the immediate data. last it will branch to e since the value in data memory is greater than that of the immediate data. chapter 11 arithmetic and logic unit (alu) 99 11.7 rotations there are rotation instructions for rotation to the right and for rotation to the left. the rorc instruction is used for rotation to the right. the rorc instruction can only be used with the general register. rotation using the rorc instruction is not affected by the bcd or cmp flags in the program status word (psword) and does not affect the z flag in the program status word (psword). rotation to the left is performed by using the addition instruction addc. 11.7.1 and 11.7.2 explain rotation. 11.7.1 rotation to the right the instruction used for rotation to the right (rorc r) rotates the contents of the general register in the direction of its least significant bit. when this instruction is executed, the contents of the cy flag becomes the most significant bit of the general register (bit 3) and the least significant bit of the general register is placed in the cy flag. example 1. mov psw, #0100b ; sets cy flag to 1. mov r1, #1001b rorc r1 when these instructions are executed, the following operation is performed. basically, when rotation to the right is performed, the following operation is executed: cy flag ? b 3 , b 3 ? b 2 , b 2 ? b 1 , b 1 ? b 0 , b ? cy flag. 2. mov psw, #0000b ; resets cy flag to 0. mov r1, #1000b ; msb mov r2, #0100b mov r3, #0010b ; lsb rorc r1 rorc r2 rorc r3 the program code above rotates the 13 bits in r1, r2, and r3 to the right. 11100 cy flag b 3 b 2 b 1 b 0 chapter 11 arithmetic and logic unit (alu) 100 11.7.2 rotation to the left rotation to the left is performed by using the addition instruction, addc r, m. example mov psw, #0000b ; resets cy flag to 0. mov r1, #1000b ; msb mov r2, #0100b mov r3, #0010b ; lsb addc r3, r3 addc r2, r2 addc r1, r1 skf cy or r3, #0001b the program code above rotates the 13 bits in r1, r2, and r3 to the left. chapter 12 ports 12.1 port 0a (p0a 0 , p0a 1 , p0a 2 , p0a 3 ) port 0a is a 4-bit input/output port with an output latch. it is mapped into address 70h of bank0 in data memory. the output format is cmos push-pull output. input or output can be specified in 4-bit units. input/output is specified by p0agio (bit 0 at address 2ch) in the register file. when p0agio is 0, all pins of port 0a are used as input port. if a read instruction is executed for the port register, pin statuses are read. when p0agio is 1, all pins of port 0a are used as output port and the contents written in the output latch are output to pins. if a read instruction is executed when pins are output ports, the contents of the output latch, rather than pin statuses, are fetched. port 0a contains a software-controlled pull-up resistor. p0agpu (bit 0 at address 0ch) of the register file is used to determine whether port 0a contains the pull-up resistor. when p0agpu is 1, all 4-bit pins are pulled up. if p0agpu is 0, the pull-up resistor is not contained. at reset, p0agio and p0agpu are set to 0 and all p0a pins become input ports without a pull-up resistor. the contents of the port output latch are 0. table 12-1. writing into and reading from the port register (0.70h) bank0 70h read p0a pin status p0a latch contents write possible write to the p0a latch input output pin input/output p0agio rf: 2ch, bit 0 0 1 101 chapter 12 ports 102 12.2 port 0b (p0b 0 , p0b 1 , p0b 2 , p0b 3 ) port 0b is a 4-bit input/output port with an output latch. it is mapped into address 71h of bank0 in data memory. the output format is cmos push-pull output. input or output can be specified in 4-bit units. input/ output is specified by p0bgio (bit 1 at address 2ch) in the register file. when p0bgio is 0, all pins of port 0b are used as input ports. if a read instruction is executed for the port register, pin statuses are read. when p0bgio is 1, all pins of port 0b are used as output ports. the contents written in the output latch are output to pins. if a read instruction is executed when pins are used as output ports, the contents of the output latch, rather than pin statuses, are fetched. port 0b contains a software-controlled pull-up resistor. p0bgpu (bit 1 at address 0ch) is used to determine whether or not port 0b contains a pull-up resistor. when p0bgpu is 1, all 4-bit pins are pulled up. when p0bgpu is 0, a pull-up resistor is not contained. at reset, p0bgio and p0bgpu are 0 and all p0b pins are input ports without a pull-up resistor. the value of the port 0b output latch is 0. table 12-2. writing into and reading from the port register (0.71h) bank0 71h read p0b pin status p0b latch contents input output pin input/output p0bgio rf: 2ch, bit 1 0 1 write possible write to the p0b latch chapter 12 ports 103 12.3 port 0c (p0c 0 /adc 0 , p0c 1 /adc 1 , p0c 2 /adc 2 , p0c 3 /adc 3 ) port 0c is a 4-bit input/output port with an output latch. it is mapped into address 72h of bank0 in data memory. the output format is cmos push-pull output. input or output can be specified in 1-bit unit. input/output can be specified by p0cbio0 to p0cbio3 (address 1ch) in the register file. if p0cbion is 0 (n = 0 to 3), the p0cn pins are used as input port. if a data read instruction is executed for the port register, the pin statuses are read. if p0cbion is 1 (n = 0 to 3), the p0cn pins are used as output port and the contents written in the output latch are output to pins. if a read instruction is executed when pins are used as output ports, the contents of the latch, rather than pin statuses, are fetched. at reset, p0cbio0 to p0cbio3 are 0 and all p0c pins are input ports. the contents of the port output latch are 0. port 0c can also be used as an analog input to the a/d converter. p0c0idi to p0c3idi (1bh address) in the register file are used to switch the port and analog input pin. if p0cnidi is 0 (n = 0 to 3), the p0cn/adcn pin functions as a port. if p0cnidi is 1 (n = 0 to 3), the p0cn/adcn pin functions as the analog input pin of the a/d converter. adcch0 and adcch1 (bits 1 and 0 at address 22h) in the register file are used to select the input pin for a/d conversion. to use p0c pins as a/d converter input pins, set p0cbion = 0 so that they are set as input ports. (see 13.3 a/d converter .) at reset, p0cbio0 to p0cbio3, p0c0idi to p0c3idi, adcch0, and adcch1 are set to 0 and the p0c pins are used as input ports. table 12-3. switching the port and a/d converter notes 1. normal setting when the pins are used as a/d converter analog input pins. 2. functions as an output port. at this time, the analog input voltage changes affected by the port output. when using this pin as an analog input pin, be sure to set p0cbion to 0. (n = 0 to 3) bank0 72h p0cnidi rf: 1bh pin status p0c latch contents p0c latch contents p0c latch contents input port port output a/d converter analog input note1 output port and a/d converter analog input note2 0 1 0 1 0 1 p0cbion rf: 1ch function possible p0c latch possible p0c latch possible p0c latch possible p0c latch write read chapter 12 ports 104 12.4 port 0d (p0d 0 /sck, p0d 1 /so, p0d 2 /si, p0d 3 /tm0out) port 0d is a 4-bit input/output port with an output latch. it is mapped into address 73h of bank0 in data memory. the output format is n-ch open-drain output. the mask option can be used to specify that a pin contain a pull-up resistor in 1-bit unit. input or output can be specified in 1-bit unit. input/output is specified with p0dbio0 to p0dbio3 (address 2bh) in the register file. if p0dbion is 0 (n = 0 to 3), the p0dn pins are used as input port. pin statuses are read if a data read instruction is executed for the port register. if p0dbion is 1, the p0dn pins are used as output port and the value written in the output latch are output to pins. if a data read instruction is executed when pins are used as output ports, the output latch value, rather than pin statuses, is fetched. at reset, p0dbion is set to 0 and all p0d pins become input ports. the contents of the port output latch become 0. the output latch contents remain unchanged even if p0dbion changes from 1 to 0. port 0d can also be used for serial interface input/output or timer 0 output. sioen (0bh bit 0) in the register file is used to switch ports (p0d 0 to p0d 2 ) to serial interface input/output (sck, so, si) and vice versa. tm0osel (bit 3 at address 0bh) in the register file is used to switch a port (p0d 3 ) to timer 0 output (tm0out) and vice versa. if tm0osel = 1 is selected, 1 is output at timer 0 reset. this output is inverted every time a timer 0 count value matches the modulo register contents. table 12-4. register file contents and pin functions p0d 0 /sck p0d 1 /so p0d 2 /si p0d 3 /tm0out input port output port so so si si input port output port input port output port tm0out sck sck 0 1 0 1 0 1 0 1 0 1 0 1 0 1 register file value pin function tm0osel rf: 0bh bit 3 sioen rf: 0bh bit 0 p0dbion rf: 2bh bit n (n = 0 to 3) chapter 12 ports 105 port mode input port output port si so tm0out sck contents read from the port register (0.73h) pin status output latch contents output latch contents pin status pin status not defined output latch contents an internal clock is selected as a shift clock. an external clock is selected as a shift clock. bank1 70h pin input/output (n = 0 to 3) p1agion rf: 2ch, bit 2 0 1 input output write possible write to the p1a latch read p1a pin status p1a latch contents table 12-5. contents read from the port register (0.73h) caution using the serial interface causes the output latch for the p0d 1 /so pin to be affected by the contents of the siosfr (shift register). so, reset the output latch before using the pin as output port. 12.5 port 1a (p1a 0 , p1a 1 , p1a 2 , p1a 3 ) port 1a is a 4-bit input/output port with an output latch. it is mapped into address 70h of bank1 in data memory. the output format is n-ch open-drain output. the mask option can be used to specify that a pin contain a pull-up resistor in 1-bit unit. input or output can be specified in 4-bit units. input/output is specified by p1agio (bit 2 at address 2ch) in the register file. when p1agio is 0, each pin of port 1a is used as input port. if a read instruction is executed for the port register, pin statuses are read. when p1agio is 1, each pin of port 1a is used as output port and the contents written in the output latch are output to pins. if a read instruction is executed when pins are output ports, the contents of the output latch, rather than pin statuses, are fetched. at reset, p1agio is set to 0 and all p1a pins become input ports. the contents of the port output latch are 0. table 12-6. writing into and reading from the port register (1.70h) 12.6 port 1b (p1b 0 ) port 1b is a 1-bit input-dedicated port. it is mapped into address 71h of bank1 in data memory. the mask option can be used to specify that pull-up resistors be contained in p1b 0 pins. port 1b is the input-dedicated port. at reading, only the least significant bit is valid and a value is read into it. at writing, no value changes. value 0 is always read into the high-order 3 bits of the port register. chapter 12 ports 106 12.7 port control register 12.7.1 input/output switching by group i/o ports which switch input/output in 4-bit unit are called group i/o. port 0a, port 0b, and port 1a are used as group i/o. the register shown in the figure below is used for input/output switching. figure 12-1. input/output switching by group i/o bit 3 bit 2 bit 1 bit 0 0 p1agio p0bgio p0agio r/w 0000 0 p0agio function sets port 0a to input mode. 1 sets port 0a to output mode. read/write initial value when reset 0 p0bgio function sets port 0b to input mode. 1 sets port 0b to output mode. 0 p1agio function sets port 1a to input mode. 1 sets port 1a to output mode. rf: 2ch read = r, write = w chapter 12 ports 107 12.7.2 input/output switching by bit i/o ports which switch input/output in 1-bit unit are called bit i/o. port 0c and port 0d are used as bit i/o. the register shown in the figure below is used for input/output switching. figure 12-2. port control register of bit i/o (1/2) bit 3 bit 2 bit 1 bit 0 p0cbio3 p0cbio2 p0cbio1 p0cbio0 r/w 0000 0 p0cbio0 function sets p0c 0 to input mode. 1 sets p0c 0 to output mode. read/write initial value when reset 0 p0cbio1 function sets p0c 1 to input mode. 1 sets p0c 1 to output mode. 0 p0cbio2 function sets p0c 2 to input mode. 1 sets p0c 2 to output mode 0 p0cbio3 function sets p0c 3 to input mode. 1 sets p0c 3 to output mode. rf: 1ch read = r, write = w chapter 12 ports 108 figure 12-2. port control register of bit i/o (2/2) bit 3 bit 2 bit 1 bit 0 p0dbio3 p0dbio2 p0dbio1 p0dbio0 r/w 0000 0 p0dbio0 function sets p0d 0 to input mode. 1 sets p0d 0 to output mode. read/write initial value when reset 0 p0dbio1 function sets p0d 1 to input mode. 1 sets p0d 1 to output mode. 0 p0dbio2 function sets p0d 2 to input mode. 1 sets p0d 2 to output mode. 0 p0dbio3 function sets p0d 3 to input mode. 1 sets p0d 3 to output mode. rf: 2bh read = r, write = w chapter 12 ports 109 12.7.3 specifying pull-up resistor incorporation using software pull-up resistor incorporation can be specified in 4-bit units using p0agpu and p0bgpu (address 0ch) in the register file. figure 12-3. specifying pull-up resistor incorporation using software bit 3 bit 2 bit 1 bit 0 p0bgpu p0agpu r/w 0000 0 p0agpu function does not contain pull-up resistor in port 0a. 1 read/write initial value when reset 0 p0bgpu function 1 rf: 0ch read = r, write = w 0 0 does not contain pull-up resistor in port 0b. contains pull-up resistor in port 0a. contains pull-up resistor in port 0b. [memo] 110 chapter 13 peripheral hardware 13.1 8-bit timers/counters (tm0 and tm1) the m pd17134a subseries has two channels of 8-bit timers/counters: timer 0 (tm0) and timer 1 (tm1). these two timers can be used in combination as a 16-bit timer by using the count up signal of timer 0 as the count pulse for timer 1. these timers are controlled by manipulating the hardware with the put/get instruction and registers in the register file with the peek/poke instruction. 13.1.1 8-bit timers/counters configuration figure 13-1 shows the configuration of the 8-bit timers/counters. an 8-bit timer/counter consists of an 8-bit count register, 8-bit modulo register, a comparator that compares the value of the count register and the value of the modulo register, and a selector that selects a count pulse. cautions 1. the modulo register is a write-only register. 2. the count register is a read-only register. 111 chapter 13 peripheral hardware 112 figure 13-1. configuration of the 8-bit timer counters data buffer (dbf) internal bus tm0en tm0res tm0ck1 tm0ck0 int tm0osel p0dbio3 zcross 2 ac zero cross detection circuit control register (rf : 1dh) interrupt control register (rf : 0fh) timer 0 mode register (rf : 11h) serial inter- face control register (rf : 0bh) bit i/o port control register ( rf : 2bh) timer 0 modulo register (8) (tm0m) latch dq clk r reset selec- tor f x /256 f x /64 f x /16 int internal reset to basic interval timer ac zero cross detection circuit clear irqtm0 clear signal timer 0 count up signal (to timer 1 and basic interval timer) irqtm0 set signal p0d 3 / tm0out reset match tm0out f/f p0db 3 output latch data buffer (dbf) internal bus timer 1 mode register (rf : 12h) tm1en tm1res tm1ck1 tm1ck0 2 d clk q r latch reset clear timer 1 count register (8) (tm1c) timer 1 modulo register (8) (tm1m) timer 1 comparator (8) match f x /512 f x /1024 f x /256 timer 0 count up selector irqtm1 set signal irqtm1 clear signal internal reset timer 0 comparator (8) timer 0 count register (8) (tm0c) chapter 13 peripheral hardware 113 figure 13-2. timer 0 mode register rf : 11h read/write initial value when reset bit 3 tm0en 0 bit 2 tm0res 0 bit 1 tm0ck1 0 bit 0 tm0ck0 0 r/w read = r, write = w tm0ck1 0 0 1 1 tm0ck0 0 1 0 1 selects count pulse of timer 0 f x /256 f x /64 f x /16 external clock from int pin tm0res 0 resets timer 0 does not affect timer 0 resets timer 0 count register and irqtm0 1 tm0en 0 1 starts timer 0 stops counting by timer 0 starts counting by timer 0 remark tm0res is automatically cleared to 0 after it has been set to 1. this bit is always 0 when it is read. remark tm0en can be used as a status flag that detects the counting status of timer 0 (1: counting in progress, 0: counting is stopped). chapter 13 peripheral hardware 114 figure 13-3. timer 1 mode register rf : 12h read/write initial value when reset bit 3 tm1en 1 r/w bit 2 tm1res 0 bit 1 tm1ck1 0 bit 0 tm1ck0 0 tm1ck1 0 0 1 1 tm1ck0 0 1 0 1 selects count pulse of timer 1 f x /512 f x /1024 f x /256 count up signal from timer 0 tm1res 0 resets timer 1 does not affect timer 1 resets timer 1 count register and irqtm 1 1 tm1en 0 1 starts timer 1 stops counting by timer 1 starts counting by timer 1 remark remark tm1en can be used as a status flag that detects the counting status of timer 0 (1: counting in progress, 0: counting is stopped). tm1res is automatically cleared to 0 after it has been set to 1. this bit is always 0 when it is read. chapter 13 peripheral hardware 115 13.1.2 operation of 8-bit timers/counters (1) count register the count register of timers 0 and 1 is an 8-bit up counter whose initial value is 00h, and is incremented each time a count pulse has been input. the count register is initialized to 00h in the following cases. (1) when this product is reset (refer to chapter 17 reset ). (2) when the contents of the 8-bit modulo register and the value of the count register coincide, and the comparator generates a coincidence signal. (3) in the case of timer 0, when 1 is written to tm0res of the register file. in the case of timer 1, when 1 is written to tm1res of the register file. (2) modulo register the modulo register of timers 0 and 1 determines the count value of the count register and its initial value is set to ffh. a value is set to the modulo register by using the put instruction via dbf (data buffer). (3) comparator the comparator of timers 0 and 1 outputs a coincidence signal when the value of the count register and the value of the modulo register coincide. if the value of the modulo register is the initial value ffh, for example, the comparator outputs the coincidence signal when the count register counts 256. the coincidence signal output from the comparator clears the contents of the count register to 0, and automatically sets interrupt request flags (irqtm0 and irqtm1) to 1. if the ei instruction (that enables accepting interrupts) is executed, and if the interrupt enable flags (iptm0 and iptm1) are set at this time, interrupts are accepted. when an interrupt has been accepted, the interrupt request flag (irqtm0 or irqtm1) is cleared to 0, and program execution branches to a specified interrupt routine. 13.1.3 selecting count pulse the count pulse for timer 0 is selected by tm0ck0 and tm0ck1. as the count pulse, a pulse resulting from dividing the system clock (f x ) by 256, 64, or 16, or an external count pulse input from the int pin can be selected. at reset, f x /256 is selected as a count pulse because tm0ck0 = 0 and tm0ck1 = 0. the count pulse for timer 1 is selected by tm1ck0 and tm1ck1. as the count pulse, a pulse resulting from dividing f x by 1024, 512, or 256, or the count up signal from timer 0 can be selected. timer 1 is also used to generate oscillation stabilization time on power application or at reset. therefore, the initial values are tm1ck0 = 0 and tm1ck1 = 0, and f x /512 is selected as the count pulse. because tm1en = 1 as the initial condition, the m pd17134a subseries starts program execution from address 0000h after it has been reset at f x = 8 mhz and after about 16.4 ms (about 65.5 ms at 2 mhz) (refer to chapter 17 reset ). chapter 13 peripheral hardware 116 13.1.4 setting count value to modulo register a value is set to the modulo register by using the put instruction via dbf (data buffer). the peripheral address of the modulo register of timer 0 is assigned to 02h, and that of timer 1 is assigned to 03h. to transfer a value by using the put instruction, the data of the low-order 8 bits of dbf (dbf1 and dbf0) are transferred to the modulo register. figure 13-4 shows an example of the modulo register of timer 0. figure 13-4. setting count value to modulo register example of setting count value 64h to modulo register of timer 0 contdatl dat 4h ; assigns contdatl to 4h by using symbol definition instruction contdath dat 6h ; assigns contdath to 6h by using symbol definition instruction mov dbf0, #contdatl ; mov dbf1, #contdath ; put tm0m, dbf ; transfers data by using reserved word tm0m b 7 8-bit data put tm0m, dbf tm0m (peripheral address 02h) b 6 b 5 b 4 b 3 b 2 b 1 b 0 01100100 dbf3 dbf2 dbf1 dbf0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 don? care don? care 0 1 1 0 0 1 0 0 data buffer caution the range of the value to that can be set to the modulo register is 01h to ffh. if 00h is set, the normal count operation is not performed. the modulo register is a write-only register. therefore, the set value of the modulo register cannot be read. even if the put tm0m, dbf or put tm1m, dbf instruction is executed while the 8-bit timer/counter is operating, the count is operating is not stopped. chapter 13 peripheral hardware 117 13.1.5 reading value of count register the values of the count registers of timers 0 and 1 are read simultaneously by using the get instruction via dbf (data buffer). the values of the count registers of timers 0 and 1 are assigned to peripheral address 45h. the high-order 8 bits of this address are assigned to the count value of timer 1, and the low-order 8 bits are assigned to the count value of timer 0. the values of the count registers can be read to dbf by using the get instruction. while the get instruction is being executed, the count registers stop counting and hold the current count value. if a count pulse is input to the timer while the timer is operating and the get instruction is being executed, the count value is held, the value of the count register is incremented by one after the get instruction has been executed, and the timer continues counting. therefore, the timer does not count erroneously even if the get instruction is executed while the timer is operating, unless two or more count pulses are input to the timer in one instruction cycle. figure 13-5. reading count value of count register example of using get dbf, tm0tm1c; reserved word dbf and tm0tm1c when count value of timer 0 is f0h and count value of timer 1 is a4h data buffer dbf3 dbf2 dbf1 dbf0 1010010011110000 16-bit data get dbf, tm0tm1c b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1010010011110000 tm0tm1c (peripheral address) timer 0 count value timer 1 count value chapter 13 peripheral hardware 118 13.1.6 setting of interval time the time interval at which the comparator outputs the coincidence signal is determined by the value set to the modulo register. the set value n of the modulo register is calculated from interval time t [sec] as follows: t = n + 1 = (n + 1) t cp f cp n = t f cp C 1 or n = t C 1 (where, n = 1 to 255) tcp f cp : frequency of count pulse [hz] t cp : cycle of count pulse [sec] (1/f cp = resolution) ? example of calculating count value from interval time and program ? example of setting 7 ms to timer 1 as interval time (system clock: f x = 8 mhz) suppose one wanted to set the interval timer to 7 ms. it is impossible to set an interval time of exactly 7 ms from an 8-mhz system clock. to set an interval time closest to 7 ms, therefore, calculate the count value by selecting a count pulse (f x /256, resolution: 32 m s) at which the resolution is maximum. example of calculation t = 7 ms, resolution = 32 m s n= t C 1 (resolution) = 7 10 C3 C 1 32 10 C6 = 217.75 = 218 (= dah) the value of the modulo register at which the interval time is closest to 7 ms is dah, and the interval time at that time is 7.008 ms. program example mov dbf0, #0ah ; stores dah to dbf by using reserved words dbf0 and dbf1 mov dbf1, #0dh ; storage put tmm, dbf ; transfers contents of dbf by using reserved word tmm initflg tm1en, tm1res, tm1ck1, not tm1ck0 ; sets tm1en and tm1res, sets count pulse of timer 1 to f x /256, and starts ; counting, by using embedded macroinstruction initflg . . chapter 13 peripheral hardware 119 13.1.7 error of interval time the interval time may include an error of up to C1.5 count, especially if the value set value of the modulo register is low. (1) error when count register is cleared to 0 during counting (maximum error: C1 count) the count register of the 8-bit timer/counter is cleared to 0 when the tmnres flag is set to 1. however, the divider circuit that generates a count pulse from the system clock is not reset. therefore, an error of 1 cycle of the count pulse may be generated at the first count if the tmnres flag is set to 1 and the count value is cleared to 0 during counting. an example of counting where 2 is set to the modulo register is shown below. figure 13-6. error when count register is cleared to 0 during counting in this example, the coincidence signal must be output each time the count value has reached 3. however, the coincidence signal is output when the count value reaches 2 for the first time after the count has been cleared. the above error also occurs when tmnres ? 1 at the same time as tmnen = 1 ? 0. 12 0 1 2 count register count pulse output of coincidence signal count cleared (tmnres ? 0) 2 to 3 counts chapter 13 peripheral hardware 120 (b) if counting is started when count pulse is low (error: e1 to e1.5 count) in this example, the coincidence signal must be output each time the count value has reached 2. however, the first coincidence signal is output when the count value is 1.5 at maximum or 0.5 at minimum (error: C0.5 to C1.5 count). the above error also occurs during oscillation stabilization wait time because the timer is also used to generate the oscillation stabilization wait time. 0101 count register count pulse coincidence signal output count starts (tmnen = 1 ? 0) 2 counts coincidence signal output 1 to 1.5 count (2) error when counting is started from count stop status (maximum error: ?.5 count) the count register of the 8-bit timer is cleared to 0 by setting the tmnres flag to 1. however, the divider circuit that generates a count pulse from the system clock is not reset. if the tmnen flag is set to 1 and counting is started from the count stop status, the timing of the first counting differs as follows depending on whether the count pulse starts with a low level or a high level. if count pulse starts with high level: first count at the next rising if count pulse starts with low level: first count on starting of counting therefore, an error of C0.5 to 1.5 count occurs until the coincidence signal is output for the first time after counting has been started. an example of counting where the modulo register is set to 1 is shown below. figure 13-7. error when counting is started from count stop status (a) if counting is started when count pulse is high (error: C0.5 to C1 count) 01 00 count register count pulse coincidence signal output count starts (tmnen = 1 ? 0) 2 counts coincidence signal output 0.5 to 1 count 1 chapter 13 peripheral hardware 121 13.1.8 timer 0 output the pod 3 /tm0out pin functions as timer 0 output pin by setting the tm0osel flag to 1. at this time, the value of p0dbio3 is irrelevant. timer 0 has an internal flip-flop for outputting a coincidence signal. the output of this flip-flop is inverted each time the comparator has output the coincidence signal. if the tm0osel flag is set to 1, the content of this flip-flop is output to the p0d 3 /tm0out pin. the p0d 3 /tm0out pin is an n-ch open-drain output pin and can be connected to a pull-up resistor by mask option. if the pull-up resistor is not connected, the p0d 3 /tm0out pin goes into a high-impedance state as the initial status. the internal timer 0 output flip-flop starts operating as soon as tm0en has been set to 1. to make sure that timer 0 output always starts from the initial status, set tm0res to 1 and reset the flip-flop before starting counting. figure 13-8. timer 0 output setting register bit 3 tm0osel 0 bit 2 0 0 bit 1 0 0 bit 0 sioen 0 read/write initial value when reset r/w read = r, write = w rf : 0bh function p0d 0 /sck, p0d 1 /so, and p0d 2 /si pins function as port pins. p0d 0 /sck, p0d 1 /so, and p0d 2 /si pins function as serial interface pins. sioen 0 1 function p0d 3 /tm0out pin functions as port pin. p0d 3 /tm0out pin outputs coincidence signal of timer 0. tm0osel 0 1 caution this bit is not directly related to output setting of timer 0. chapter 13 peripheral hardware 122 13.2 basic interval timer (btm) the m pd17134a subseries has a 7-bit basic interval timer. this basic interval timer has the following functions. (1) generates reference time. (2) selects and counts wait time when standby mode is released. (3) serves as watchdog timer that detects program hang-up. 13.2.1 basic interval timer configuration figure 13-9 shows the configuration of the basic interval timer. figure 13-9. basic interval timer configuration remark (1) through (4) in the figure corresponding to the signals in the timing chart in figure 13-12. btm mode register (rf: 13h) watchdog timer mode register (rf: 03h) btmisel btmres btmck1 btmck0 wdtres 0 0 wdten 2 reset selector f x /8192 f x /4096 timer 0 count up int pin (aczcross) basic interval timer (7-bit divider circuit) reset selector irqbtm set signal watchdog reset signal r s (3) (2) outputs 1 while counting 0 to 7 during count of 0 to 256 f btm 2 7 f btm 2 6 f btm q 1-bit divider circuit 1-shot pulse generation circuit internal bus (4) (1) chapter 13 peripheral hardware 123 13.2.2 registers controlling basic interval timer the basic interval timer is controlled by the btm mode register and watchdog timer mode register. figures 13-10 and 13-11 show the configuration of the respective registers. figure 13-10. btm mode register bit 3 btmisel 0 bit 2 btmres 0 bit 1 btmck1 0 bit 0 btmck0 0 read/write initial value when reset r/w selects count pulse of btm f x /8192 (execution time of 512 instructions) f x /4096 (execution time of 256 instructions) count up of timer 0 int pin (information on int pin that has gone through ac zero cross detection circuit when zcross = 1) btmck1 0 0 1 1 btmck0 0 1 0 1 resets btm does not affect basic interval timer (btm). resets binary counter of basic interval timer (btm). btmres 0 1 selects interval time sets count pulse divided by 128 as interval time. sets count pulse divided by 32 as interval time. btmisel 0 1 remark read = r, write = w rf : 13h btmres is automatically cleared to 0 after it has been set to 1. this bit is always ??when it is read. chapter 13 peripheral hardware 124 figure 13-11. watchdog timer mode register 13.2.3 operation of basic interval timer the basic interval timer is a 7-bit binary counter that always counts up by using a count pulse specified by the btm mode register. counting operation cannot be stopped. the interval time of the basic interval timer can be changed by using the btmisel bit of the btm mode register. when btmisel = 0, the interval time is the count pulse divided by 128 (128/f btm ); when btmisel = 1, the interval time is the count pulse divided by 32 (32/f btm ). the contents of the counter are not cleared to 0 even if the interval time is changed. bit 3 wdtres 0 bit 2 0 0 bit 1 0 0 bit 0 wdten 0 read/write initial value at reset r/w read = r, write = w rf : 03h wdten 0 1 does not affect watchdog timer. sets flip-flop that holds overflow carry of btm used by watchdog timer. wdtres 0 1 enables watchdog timer function watchdog timer stops. watchdog timer starts operating. resets watchdog timer remarks 1. wdten cannot be cleared to 0 by program. 2. wdten is automatically cleared to 0 after it has been set to 1. this bit is always 0 when it is read. remark wdtres is automatically cleared to 0 after it has been set to 1. this bit is always 0 when it is read. chapter 13 peripheral hardware 125 13.2.4 watchdog timer function the basic interval timer can also be used as a watchdog timer to detect a program hang-up. (1) function of watchdog timer the watchdog timer is a counter that generates a reset signal at fixed intervals. by inhibiting the generation of this reset signal each time through program, the system can be reset (and started from address 0000h) if it has overrun due to an external noise (i.e., if the watchdog timer is not reset within the time set by program). this function can prevent the system from overrunning even if the program is caused to jump to an unexpected routine by an external noise and enter an infinite loop, because a reset signal is generated at fixed intervals. (2) operation of the watchdog timer when 1 is set to wdten, the 1-bit divider is enabled to operate, and consequently, the basic interval timer operates as an 8-bit watchdog timer. once the watchdog timer has been started, it cannot be stopped until the device is reset and wdten is cleared to 0. generation of the reset signal by the watchdog timer can be inhibited in the following two ways: (i) repeat setting wdtres in program. (ii) repeat setting btmres in program. in the case of (i), wdtres must be set while the count value of the watchdog timer is between 8 and 191 (immediately before it reaches 192). therefore, set1 wdtres must be executed at least once at a timing shorter than the cycle in which the count value of the watchdog timer reaches 184. in the case of (ii), btmres must be set until the count value of the basic interval timer (btm) reaches 128. therefore, set btmres must be executed at least once at a timing shorter than the cycle in which the count value of btm reaches 128. in this case, however, interrupt processing cannot be performed by btm. caution btm is not reset even if wdten is set. therefore, be sure to set btmres and reset btm before setting wdten first. example set1 btmres set2 wdten, wdtres . . . . . . chapter 13 peripheral hardware 126 figure 13-12. timing chart of watchdog timer (with wdtres flag used) wdten 8 reset signal is not generated count value of watchdog timer wdtres 1-shot pulse generator circuit output (1) (4) f btm /2 7 (2) ( irqbtm set) f btm /2 8 (3) watchdog reset signal (active high) wdtres accepting period wdtres accepting period wdtres accepting period 128 192 255 0 8 128 192 255 8 128 192 64 128 192 255 chapter 13 peripheral hardware 127 (3) program example of watchdog timer program example notes 1. interrupt processing by btm cannot be performed in the method to reset counter before btm overflows. 2. although the method of resetting the watchdog timer by using the btm interrupt processing is easier to program than the other two methods, its program hang-up detection rate is lower than that of the other two. start initialize main processing org br org br initjob: initflg set1 set2 set1 clr1 ei ...... main: call call ...... end ......................... .......... .......... job1: clr1 ipbtm set1 btmres .......... .......... set1 btmres set1 btmres .......... set ipbtm ret job2: clr2 ipbtm set1 wdtres set ipbtm ret set1 wdtres intbtmjob: set1 wdtres ei reti reset btm before its count value reaches to 128 note 1 . reset watchdog timer before its count value reaches to 184. reset watchdog timer by using interrupt processing of btm note 2 . ; btm interrupt enable .......... 0h initjob 2h intbtmjob not btmisel, btmres, not btmck1, btmck0 btmres wdtres, wdten; watchdog timer start ipbtm irqbtm job1 job2 chapter 13 peripheral hardware 128 13.3 a/d converter m pd17134a subseries contains an 8-bit resolution a/d converter with 4-channel analog input (p0c 0 /adc 0 - p0c 3 / adc 3 ). the a/d converter uses the successive approximation method. the following two operation modes are available: (1) successive mode: 8-bit a/d conversion occurs starting at high-order bits. (2) single mode: comparison occurs with an arbitrary voltage value set in the 8-bit data register. 13.3.1 a/d converter configuration figure 13-13 shows the a/d converter configuration. figure 13-13. block diagram of the a/d converter cautions 1. the 8-bit data register (adcr) is cleared to 00h when the stop instruction has been executed. 2. if the halt instruction is executed during a/d conversion, a current keeps flowing between v adc and gnd. adcsoft adccmp adcend adcstrt 00 0 adcch1 0 adcch0 rf : 20h rf : 21h internal bus 00 rf : 22h remark n = 0 to 3 read signal p0cnidi p0cbion p0cn/adcn v adc selector output latch selector 4 3r/2 r r r/2 tap decoder comparator d/a converter 8-bit data register (adcr) 8 control circuit 8 a/d end signal stop instruction signal analog power of a/d converter chapter 13 peripheral hardware 129 13.3.2 functions of a/d converter (1) adc 0 e adc 3 these pins are used to input 4-channel analog voltage to the a/d converter. the a/d converter contains a sample hold circuit. analog input voltage is internally retained during a/d conversion. (2) v adc this pin is used to input the power supply and the reference voltage for the a/d converter. a signal input to adc 0 to adc 3 is converted to a digital signal based on voltage applied across v adc and gnd. to reduce the current consumption of the microcontroller, the a/d converter has a function for automatically stopping the current which flows into the v adc pin when the converter is not operating. current flows into the v adc pin in the following cases. <1> successive mode (adcsoft=0) from when the adcstrt flag is set (1) until the adcend flag is set (1). <2> single mode (adcsoft=1) from when the adcstrt flag is set (1) or from when a value of the 8-bit data register is written until the result of comparison by the comparator is written in the adccmp flag. caution if the halt instruction is executed while the a/d conversion is in progress, the a/d converter stops conversion. note that, in this case, the halt mode is set with current flowing to the v adc pin. when the halt mode has been released, the a/d conversion is resumed. at this time, however, the value of adcr is undefined, and the correct conversion result cannot be obtained. remark a/d conversion is stopped if the stop instruction is executed while the conversion is in progress. in this case, the a/d converter is initialized, and the current to the v adc pin is also cut. the a/d converter remains stopped even if the stop mode has been released. (3) 8-bit data register (adcr) in the successive mode, this 8-bit data register stores a/d conversion results for successive approximation. it is read by the get instruction. in the single mode, the data in this register is converted to analog voltage by the internal d/a converter and the comparator compares this voltage with an analog signal input from the adcn pin. a value can be written in this register by using the put instruction. (4) comparator the comparator compares an analog input voltage from a pin with voltage output from the d/a converter. value 1 is output if analog input voltage from the pin is high. value 0 is output if this voltage is low. the comparison result is stored in the 8-bit data register (adcr) in the successive mode. it is stored in the adccmp flag in the single mode. (5) a/d converter control register figure 13-14 shows the a/d converter control register. chapter 13 peripheral hardware 130 figure 13-14. a/d converter control register (1/2) remarks 1. in the single mode, the flag content is valid for the third and subsequent in- structions after adcstrt is set (1) or data is set in adcr until adcstrt or adcr is set again. 2. in the successive mode, a value changes according to an a/d conversion value. however, the bit for this value cannot be identified. 3. adccmp is automatically cleared to 0 when put adcr, dbf instruction is executed. bit 3 bit 2 bit 1 bit 0 r/w 0 00 0 0 adcend end of a/d conversion read/write initial value when reset 0 adccmp compare result (valid only in the single mode) 1 0 adcsoft a/d operation mode selection flag successive mode 1 single mode rf: 21h read = r, write = w adcsoft 0 adccmp adcend 1 r initial status or during a/d conversion. indicates the end of a/d conversion in successive mode. cleared to 0 by setting (1) or resetting adcstrt. analog input voltage is lower than output voltage of the internal d/a converter. analog input voltage is higher than output voltage of the internal d/a converter. chapter 13 peripheral hardware 131 figure 13-14. a/d converter control register (2/2) note with the m pd17134a subseries, adcr is reset to 0 if the adcstrt flag is set, regardless of the a/d conversion mode. in the single mode, start conversion by writing a value to adcr. 0 0 adcstrt start of a/d operation 1 rf: 20 h read = r, write = w bit 3 bit 2 bit 1 bit 0 r/w 00 0 read/write initial value when reset adcstrt 00 0 initial status or during a/d conversion. cleared to 0 automatically after a/d conversion (successive or single mode note ) starts. 0 adcch1 analog input channel selection adc 0 is selected. 0 adc 1 is selected. rf: 22h read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w adcch3 adcch2 read/write initial value when reset adcch0 000 adcch1 0 1 adcch0 1 1 0 1 adc 2 is selected. adc 3 is selected. fixed to 0. (dummy flag) chapter 13 peripheral hardware 132 13.3.3 setting values in the 8-bit data register (adcr) a value is set in the 8-bit data register via the data buffer (dbf) using the put instruction in the same way as for comparison voltage setting in the single mode. the peripheral address for the 8-bit data register (adcr) of the a/d converter is assigned to 04h. if a value is sent to adcr by the put instruction, only the low-order 8 bits (dbf1, dbf0) of dbf are valid. dbf3 and dbf2 values do not affect adcr. figure 13-15. setting a value in the 8-bit data register (adcr) example of setting 6ch in adcr contdatl dat 0ch ; contdatl is assigned to 0ch by using a symbol definition instruction. contdath dat 06h ; contdath is assigned to 06h by using a symbol definition instruction. mov dbf0, #contdatl; mov dbf1, #contdath; put adcr, dbf ; data is transferred using reserved words adcr and dbf. dbf3 dbf2 dbf1 dbf0 01101100 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 don't care don't care 01101100 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 put adcr, dbf data buffer 8-bit data adcr (peripheral address 04h) chapter 13 peripheral hardware 133 13.3.4 reading values from the 8-bit data register (adcr) a value is read from the 8-bit data register (adcr) via the data buffer (dbf) using the get instruction. the 8-bit data register (adcr) of the a/d converter has peripheral address 04h and only its low-order 8 bits (dbf1, dbf0) are valid. execution of the get instruction does not affect the high-order 8 bits of dbf. figure 13-16. reading values from the 8-bit data register (adcr) the result from 8-bit a/d conversion is e2h. get dbf, adcr ; example of using reserved words dbf and adcr dbf3 dbf2 dbf1 dbf0 11100010 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 retained retained 11100010 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 get dbf, adcr data buffer 8-bit data adcr (peripheral address 04h) chapter 13 peripheral hardware 134 13.3.5 a/d converter operation the a/d converter operates in two modes: successive mode and single mode. the mode can be switched by setting the adcsoft flag. adcsoft operation mode of a/d converter 0 successive mode (a/d conversion) 1 single mode (compare operation) figure 13-17. relationship between the analog input voltage and digital conversion result ffh feh fdh n 03h 02h 01h 1 256 2 256 n 256 254 256 255 256 256 256 00h 0 ( v dd ) digital conversion result analog input voltage (v) ideal conversion result chapter 13 peripheral hardware 135 (1) successive mode (a) outline of successive mode in the successive mode, the a/d converter performs conversion in 8-bit units by means of successive approximation, and the result of the conversion is automatically stored to an 8-bit data register (adcr). an analog input voltage and the voltage output by the internal d/a converter are compared by the internal comparator, and data for conversion is sequentially obtained from 8 bits of data, starting from the most significant bit. a time of 25 instructions is required to complete converting the 8 bits of data. the completion of the 8-bit a/d conversion is indicated by setting of the adcend flag to 1. (b) operation in successive mode when adcsoft = 0, the a/d converter is set in the successive mode. by setting p0cnidi to 1 before starting a/d conversion, use of a pin used as an analog input pin of the a/d converter as a port pin is prohibited. this is to prevent an increase in the through current of the input buffer of the port if the voltage of the pin specified as an analog input pin reaches the intermediate level. after that, an analog input signal is selected by adcch1 and adcch0. a/d conversion is started by setting the adcstrt flag to 1. the adcstrt flag is cleared to 0 immediately after a/d conversion has been started. while a/d conversion is in progress, the internal hardware performs successive approximation, starting from the most significant bit of the 8 bits of data. the conversion result is stored to an 8-bit data register on a bit-by-bit basis. converting 1 bit of data requires a time of three instructions. if a resolution of 8 bits is not required, therefore, the time required can be calculated from the number of instructions executed, and the data being converted can be extracted before the adcend flag is set. the completion of the a/d conversion is indicated by setting of the adcend flag which takes place as soon as data has been stored to the least significant bit of the 8-bit data register. chapter 13 peripheral hardware 136 figure 13-18. using the successive mode for the a/d converter set the successive mode (adcsoft = 0) set the port input disable flag of the pin used for analog input (set p0cnidi to 1. n = 0 to 3) select the analog input channel (set adcch1 or adcch0) start a/d conversion (set adcstrt to 1) wait for the completion of a/d conversion (wait for adcend to be set) read the a/d conversion results (execute get for the 8-bit data register) chapter 13 peripheral hardware 137 (c) successive mode a/d conversion timing figure 13-16 shows the a/d conversion timing in the successive mode. figure 13-19. a/d conversion timing in the continuous mode caution sampling is executed eight times while a/d conversion is performed once. therefore, if the analog input voltage changes substantially during a/d conversion, conversion is not performed accurately. to obtain the accurate conversion result, it is necessary to keep changes in the analog input voltage as small as possible during a/d conversion. one sampling time = 14/f x (1.75 m s, 8 mhz note ) sampling repeat cycle = 48/f x (6 m s, 8 mhz note ) note the guaranteed oscillation range of the m pd17134a, 17136a, and 17p136a is 400 khz to 2.4 mhz. number of instruction to be executed (instruction cycle) poke 123456789 24get read adcr sampling sampling sampling set adcstrt previous data initial value 80h most significant bit determined high-order 2 bits are determined adcstrt adcend 8-bit data register all eight bits are vaild. chapter 13 peripheral hardware 138 table 13-1. data conversion time for the a/d converter note includes get instruction to read data from adcr. (2) single mode (a) overview of single mode in the single mode, data in the 8-bit data register (adcr) is compared with voltage subjected to d/a conversion and with an analog input signal from a pin. the comparison result appears in the adccmp flag. (b) explanation of single mode operation if adcsoft is 1, the a/d converter function enters the single mode. before single mode operation starts, port input is disabled for the pin to be used for analog input by setting p0cnidi to 1. (this is done for the same reason as in the successive mode.) to start single mode operation, execute a write instruction (put adcr, dbf) for the 8-bit data register (adcr) when adcsoft is 1. the comparison result in single mode appears in adccmp at the execution of the third instruction after a put instruction is executed to write to the 8-bit data register (adcr). at this time, the adcend flag becomes undefined. bits for which a/d conversion is completed (valid bits when adcr is read) most significant bit high-order 2 bits high-order 3 bits high-order 4 bits high-order 5 bits high-order 6 bits high-order 7 bits all 8 bits number of instructions executed after adcstrt is set to 1 note 4 instructions 7 instructions 10 instructions 13 instructions 16 instructions 19 instructions 22 instructions 25 instructions chapter 13 peripheral hardware 139 figure 13-20. using the single mode for the a/d converter set single mode (adcsoft = 1) disable port input for pin to be used for analog input (set p0cnidi to 1) select analog input channel (set adcch0 or adcch1) comparison data in adcr? read adccmp flag when third instruction is executed and read comparison result execute write instruction for 8-bit data register (put adcr, dbf) read the contents of adcr into dbf (get dbf, adcr) set comparison data in dbf no yes chapter 13 peripheral hardware 140 (c) single mode operation (comparison) timing figure 13-21. single mode operation (comparison) timing in the single mode, comparison is started when compare data is set to adcr (by executing the put instruction), and the result of conversion can be read by using the peek instruction after execution of the third instruction. the adccmp flag is cleared to 0 when an instruction that writes adcr is executed. caution before setting a value to adcr, be sure to set adcsoft to 1. a value cannot be set to adcr while adcsoft is 0 (the put adcr, dbf instruction is invalidated). one sampling time = 14/f x (1.75 m s, f x = 8 mhz) put 1 2 peek put 1 set comparison data in adcr. previous data number of instruction executed (instruction cycle) adccmp adcend 2 peek set comparison data in adcr. comparison result comparison result undefined sampling sampling read adccmp. read adccmp. chapter 13 peripheral hardware 141 13.4 serial interface (sio) the serial interface consists of an shift register (siosfr, 8 bits), serial mode register, and serial clock counter. it is used for serial data input/output. 13.4.1 functions of the serial interface this serial interface provides three signal lines: serial clock input pin (sck), serial data output pin (so), and serial data input pin (si). it allows 8 bits to be sent or received in synchronization with clocks. it can be connected to peripheral input/output devices using any method with a mode compatible to that used by the m pd7500 series or 75x series. (1) serial clock three types of internal clocks and one type of external clock are able to be selected. if an internal clock is selected as a shift clock, it is automatically output to the p0d 0 /sck pin. table 13-2. serial clock list siock1 siock0 serial clock to be selected 0 0 external clock from sck pin 01f x /16 10f x /128 11f x /1024 f x : system clock oscillation frequency (2) transfer operation each pin of port 0d (p0d 0 /sck, p0d 1 /so, and p0d 2 /si) functions as a serial interface pin when sioen is set to 1. if siots is set to 1 at this time, the operation is started in synchronization with the falling of the external or internal clock. if siots is set, irqsio is automatically cleared. transfer is started from the most significant bit of the shift register in synchronization with the falling of the serial clock, and the information on the si pin is stored to the shift register, starting from the least significant bit, in synchronization with the rising of the serial clock. when transfer of 8-bit data has been completed, siots is automatically cleared, and irqsio is set. remark when executing serial transfer, transfer is started only from the most significant bit of the shift register. it cannot be started from the least significant bit. the status of the si pin is loaded to the shift register in synchronization with the rising of the serial clock. chapter 13 peripheral hardware 142 figure 13-22. block diagram of the serial interface note the output latch of the shift register is shared with p0d 1 . if an output instruction is executed to p0d 1 , therefore, the status of the output latch of the shift register is accordingly changed. shift register (siosfr) f sys /1024 f sys /128 f sys /16 p0d 2 /si p0d 1 /so p0d 0 /sck sioen p0dbio0 p0dbio1 q s r output latch siots siohiz siock1 siock0 single shot clear serial clock counter irqsio clear signal irqsio set signal selector p0d 0 output latch selector serial start note clear carry msb lsb chapter 13 peripheral hardware 143 13.4.2 3-wire serial interface operation modes two modes can be used for the serial interface. if the serial interface function is selected, the p0d 2 /si pin always takes in data in synchronization with the serial clock. ? 8-bit transmission reception mode (simultaneous transmission and reception) ? 8-bit reception mode (so pin: in the high-impedance state) table 13-3. operating mode of the serial interface sioen siohiz p0d 2 /si pin p0d 1 /so pin operating mode of the serial interface 1 0 si so 8-bit transmission/reception mode 1 1 si p0d 1 (input) 8-bit reception mode 0 p0d 2 (i/o) p0d 1 (i/o) general-purpose port mode : dont care (1) clock synchronization 8-bit transmission and reception mode (simultaneous transmission and reception) serial data input/output is controlled by a serial clock. the msb of the shift register is output from the so line at a falling edge of the serial clock (sck pin signal). the contents of the shift register is shifted one bit at a rising edge and at the same time, data on the si line is loaded into the lsb of the shift register. every time the serial clock counter (3-bit counter) counts eight serial clocks, the interrupt request flag (irqsio ? 1) is set to 1. figure 13-23. timing of 8-bit transmission and reception mode (simultaneous transmission and reception) remark di: serial data input do: serial data output 12345678 sck pin si pin so pin irqsio transmission completion di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 transmission starts in synchronization with the sck pin falling edge. an instruction which writes 1 into siots is executed. (transmission start indication) chapter 13 peripheral hardware 144 (2) clock synchronization 8-bit transmission and reception mode (so pin output high impedance) the p0d 1 /so pin goes into a high-impedance state when siohiz = 1. if supply of the serial clock is started by writing 1 to siots at this time, only the reception function of the serial interface is enabled. because the p0d 1 /so pin goes into a high-impedance state, it can be used as an input port pin (p0d 1 ). figure 13-24. timing of the clock synchronization 8-bit reception mode remark di: serial data input (3) operation stop mode if the value in siots (rf: address 02h, bit 3) is 0, the serial interface enters operation stop mode. in this mode, no serial transfer occurs. in this mode, the shift register does not perform shifting and can be used as an ordinary 8-bit register. transmission starts in synchronization with an sck pin falling edge. an instruction which writes 1 into siots is executed. (transmission start indication) 12345678 sck pin si pin so pin irqsio transmission completion hi-z di7 di6 di5 di4 di3 di2 di1 di0 chapter 13 peripheral hardware 145 figure 13-25. serial interface control register (1/2) remark siots is automatically cleared to 0 when serial transmission is completed. 0 siock1 selection of the serial clock external clock (sck pin) 0f x /16 0 siohiz serial data output (so pin) 1 input port output high impedance (p0d 1 pin) 0 siots forced termination of the shift register (disables intermediate restart). 1 start of serial transfer operation at internal clock selection starts operation specifying the internal division signal of the system clock as a serial clock. at external clock selection starts operation in synchronization with an sck pin falling edge. rf: 02h read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w read/write initial value when reset siock0 000 siock1 siohiz siots 1f x /128 1f x /1024 siock0 0 1 0 1 function selection of the p0d 1 /so pin start and stop of serial transmission (at writing) chapter 13 peripheral hardware 146 figure 13-25. serial interface control register (2/2) caution this is not related to the serial interface directly. 0 sioen sio operation enable the pins p0d 0 /sck, p0d 1 /so, p0d 2 /si function as ports. 1 the pins p0d 0 /sck, p0d 1 /so, p0d 2 /si function as the serial interface. rf: 0bh read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w tm0osel 00 read/write initial value when reset sioen 00 0 tm0osel selecting function of the p0d 3 /tm0out pin the p0d 3 /tm0out pin is used as a port. the p0d 3 /tm0out pin is used for timer 0 output. 0 1 remark see also chapter 12 . chapter 13 peripheral hardware 147 13.4.3 setting values in the shift register values are set in the shift register via the data buffer (dbf) using the put instruction. the peripheral address of the shift register is 01h. when sending a value to the shift register using the put instruction, only the low-order 8 bits (dbf1, dbf0) of dbf are valid. the dbf3 and dbf2 values do not affect the shift register. figure 13-26. setting a value in the shift register example of setting value 64h in the shift register siodatl dat 4h ; siodatl is assigned to 4h using symbol definition. siodath dat 6h ; siodath is assigned to 6h using symbol definition. mov dbf0, #siodatl ; mov dbf1, #siodath ; put siosfr, dbf ; value is transmitted using reserved word siosfr. dbf3 dbf2 dbf1 dbf0 01100100 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 don't care don't care 01100100 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 put siosfr, dbf data buffer 8-bit data siosfr (peripheral address 01h) chapter 13 peripheral hardware 148 13.4.4 reading values from the shift register a value is read from the shift register via the data buffer (dbf) using the get instruction. the shift register has peripheral address 01h and only the low-order 8 bits (dbf1, dbf0) are valid. executing the get instruction does not affect the high-order 8 bits of dbf. figure 13-27. reading a value from the shift register get dbf, siosfr; example of using reserved words dbf and siosfr dbf3 dbf2 dbf1 dbf0 01100100 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 retained retained 01100100 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 get dbf, siosfr data buffer 8-bit data siosfr (peripheral address 01h) chapter 14 interrupt functions the m pd17134a subseries has four internal interrupt functions and one external interrupt function. it can be used in various applications. the interrupt control circuit of the m pd17134a subseries has the features listed below. this circuit enables very high-speed interrupt processing. (a) used to determine whether an interrupt can be accepted with the interrupt mask enable flag (inte) and interrupt enable flag (ip ). (b) the interrupt request flag (irq ) can be tested or cleared. (interrupt generation can be checked by software.) (c) multiple interrupts are possible (up to three levels). (d) standby mode (stop, halt) can be released by an interrupt request. (release source can be selected by the interrupt enable flag.) caution in interrupt processing, the bank register and the bcd, cmp, cy, z, and ixe flags are saved in the stack automatically by the hardware for up to three levels of multiple interrupts. the dbf and wr are not saved by the hardware when peripheral hardware such as the timers or a/d converter is accessed in interrupt processing. it is recommended that the dbf and wr be saved in ram by the software at the beginning of interrupt processing. saved data can be loaded back into the dbf and wr immediately before the end of interrupt processing. 149 chapter 14 interrupt functions 150 14.1 interrupt source types and vector addresses for every interrupt in the m pd17134a subseries, when the interrupt is accepted, a branch occurs to the vector address associated with the interrupt source. this method is called the vectored interrupt method. table 14-1 lists the interrupt source types and vector addresses. if two or more interrupts occur simultaneously, or if two or more pending interrupts are enabled at the same time, processing is performed according to the priorities shown in table 14-1. table 14-1. interrupt source types internal/ external external internal internal internal internal vector address 0005h 0004h 0003h 0002h 0001h ip flag ip rf: 2fh, bit 0 iptm0 rf: 2fh, bit 1 iptm1 rf: 2fh, bit 2 ipbtm rf: 2fh, bit 3 ipsio rf: 2eh, bit 0 ieg flag iegmd0,1 rf: 1fh C C C C remarks rising edge or falling edge can be selected. interrupt source int pin (rf: 0fh, bit 0) timer 0 timer 1 basic interval timer serial interface 1 2 3 4 5 priority irq flag irq rf: 3fh, bit 0 irqtm0 rf: 3eh, bit 0 irqtm1 rf: 3dh, bit 0 irqbtm rf: 3ch, bit 0 irqsio rf: 3bh, bit 0 chapter 14 interrupt functions 151 14.2 hardware components of the interrupt control circuit the flags of the interrupt control circuit are explained below. (1) interrupt request flag and the interrupt enable flag the interrupt request flag (irq ) is set to 1 when an interrupt request occurs. when interrupt processing is executed, the flag is automatically cleared to 0. an interrupt enable flag (ip ) is provided for each interrupt request flag. if the flag is 1, an interrupt is enabled. if it is 0, the interrupt is disabled. (2) ei/di instruction the ei/di instruction is used to determine whether an accepted interrupt is to be executed. if the ei instruction is executed, the interrupt enable flag (inte) for enabling interrupt reception is set. if the interrupt is accepted, inte is cleared to 0. since the inte flag is not registered in the register file, flag status cannot be checked by instructions. the di instruction clears the inte flag to 0 and disables all interrupts. at reset the inte flag is cleared to 0 and all interrupts are disabled. table 14-2. interrupt request flag and interrupt enable flag interrupt request flag irq irqtm0 irqtm1 irqbtm irqsio signal for setting the interrupt request flag set by edge detection of an int pin input signal. a detection edge is selected by iegmd0 or iegmd1. set by a match signal from timer 0. set by a match signal from timer 1. set by an overflow (reference time interval signal) from the basic interval timer. set by a serial data transmission end signal from the serial interface. interrupt enable flag ip iptm0 iptm1 ipbtm ipsio chapter 14 interrupt functions 152 figure 14-1. interrupt control register (1/6) note values are not latched and so change momentarily according to pin logic. once the irq flag is set, however, it remains set until an interrupt is accepted. the poke instruction to address 0fh is invalid. 0 int status of the int pin sets logical status to 0 during peek instruction execution. 1 sets logical status to 1 during peek instruction execution. rf: 0fh read = r, write = w note bit 3 bit 2 bit 1 bit 0 r 00 0 read/write initial value when reset int 000 0 iegmd1 interrupt at the rising edge rf: 1fh read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w 0 0 iegmd1 read/write initial value when reset 000 iegmd0 0 interrupt at the falling edge 1 interrupt at both edges 1 0 iegmd0 1 0 1 selection of the interrupt detection edge of the int pin chapter 14 interrupt functions 153 figure 14-1. interrupt control register (2/6) remark if tm0res is set to 1, irqtm0 is cleared to 0. 0 irq no interrupt request has been issued from the int pin or an int pin interrupt is being processed. 1 an interrupt request from the int pin occurs or an int pin interrupt is being held. 0 irq an interrupt request from the int pin is forcibly released. 1 an interrupt request from the int pin is forced to occur. rf: 3fh read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w 00 0 read/write initial value when reset irq 000 int pin interrupt request int pin interrupt request 0 irqtm0 no interrupt request has been issued from timer 0 or a timer 0 interrupt is being processed. 1 the contents of the timer 0 count register matches that of the timer 0 modulo register and an interrupt request occurs. or a timer 0 interrupt request is being held. 0 an interrupt request from timer 0 is forcibly released. 1 an interrupt request from timer 0 is forced to occur. rf: 3eh read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w 00 0 read/write initial value when reset irqtm0 000 irqtm0 tm0 interrupt request tm0 interrupt request when read when write when read when write chapter 14 interrupt functions 154 figure 14-1. interrupt control register (3/6) remark if tm1res is set to 1, irqtm1 is cleared to 0. irqtm1 is cleared to 0 also immediately after the execution of the stop instruction. remark if btmres is set to 1, irqbtm is cleared to 0. 0 irqtm1 no interrupt request has been issued from timer 1 or a timer 1 interrupt is being processed. 1 the contents of the timer 1 count register matches that of the timer 1 modulo register and an interrupt request occurs. or a timer 1 interrupt request is being held. 0 an interrupt request from timer 1 is forcibly released. 1 an interrupt request from timer 1 is forced to occur. rf: 3dh read = r, write = w 1 bit 3 bit 2 bit 1 bit 0 r/w 00 0 read/write initial value when reset irqtm1 000 irqtm1 tm1 interrupt request tm1 interrupt request 0 irqbtm no interrupt request has been issued from the basic interval timer or a basic interval timer interrupt is being processed. 1 the basic interval timer overflows and an interrupt request occurs. or a basic interval timer interrupt request is being held. 0 irqbtm an interrupt request from the basic interval timer is forcibly released. 1 an interrupt request from the basic interval timer is forced to occur. rf: 3ch read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w 00 0 read/write initial value when reset irqbtm 000 btm interrupt request btm interrupt request when read when write when read when write chapter 14 interrupt functions 155 figure 14-1. interrupt control register (4/6) serial interface transmission is completed and an interrupt request occurs. or, a serial interface 0 irqsio sio interrupt request 1 0 sio interrupt request an interrupt request from the serial interface is forcibly released. 1 an interrupt request from the serial interface is forced to occur. rf: 3bh read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w 00 0 read/write initial value when reset irqsio 000 irqsio no interrupt request has been issued from the serial interface or a serial interface interrupt is being processed. when read when write chapter 14 interrupt functions 156 figure 14-1. interrupt control register (5/6) enables an interrupt from the int pin. executes the ei instruction. if the irq flag is set to 1, executes interrupt processing. 0 ip int pin interrupt enable 1 rf: 2fh read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w ipbtm iptm1 iptm0 read/write initial value when reset ip 000 disables an interrupt from the int pin. holds an interrupt even if the irq flag is set to 1. enables an interrupt from timer 0. executes the ei instruction. if the irqtm0 flag is set to 1, executes interrupt processing. 0 iptm0 tm0 interrupt enable 1 disables an interrupt from timer 0. holds an interrupt even if the irqtm0 flag is set to 1. enables an interrupt from timer 1. executes the ei instruction. if the irqtm1 flag is set to 1, executes interrupt processing. 0 iptm1 tm1 interrupt enable 1 disables an interrupt from timer 1. holds an interrupt even if the irqtm1 flag is set to 1. enables an interrupt from the basic interval timer. executes the ei instruction. if the irqbtm flag is set to 1, executes interrupt processing. 0 ipbtm btm interrupt enable 1 disables an interrupt from the basic interval timer. holds an interrupt even if the irqbtm flag is set to 1. chapter 14 interrupt functions 157 figure 14-1. interrupt control register (6/6) rf: 2eh read = r, write = w 0 bit 3 bit 2 bit 1 bit 0 r/w 00 0 read/write initial value when reset ipsio 000 enables an interrupt from the serial interface. executes the ei instruction. if the irqsio flag is set to 1, executes interrupt processing. 0 ipsio sio interrupt enable 1 disables an interrupt from the serial interface. holds an interrupt even if the irqsio flag is set to 1. chapter 14 interrupt functions 158 14.3 interrupt sequence 14.3.1 receiving an interrupt when an interrupt is accepted, interrupt processing starts after the instruction cycle of the instruction being executed is completed. the program flow is transferred to a vector address. however, if an interrupt occurs during movt or ei instruction, or if an instruction that satisfies the skip condition is executed, the interrupt processing is started two instruction cycles later. when interrupt processing starts, one level of the address stack register is consumed to store the program return address, and one level of the interrupt stack register is consumed to save bank and psword in the system register. if two or more interrupts occur or are enabled, interrupt processing is executed in descending order of priority. a lower-priority interrupt is held until a higher-priority interrupt is processed. see priorities shown in table 14-1. figure 14-2. interrupt processing procedure no no yes hold interrupt until ip is set hold interrupt until ei instruction is executed interrupt request generation set irq ip set? ei instruction executed? (inte = 1?) clear inte flag and irq associated with accepted interrupt to 0 decrement stack pointer by 1 (sp _ 1) save contents of program counter in stack pointed to by stack pointer load vector address into program counter save psword content in interrupt stack yes chapter 14 interrupt functions 159 14.3.2 return from the interrupt routine execute the reti instruction to return from the interrupt processing routine. during the reti instruction cycle, processing in the figure below occurs. figure 14-3. return from interrupt processing caution the inte flag is not set for the reti instruction. interrupt processing is completed. to handle a pending interrupt successively, execute the ei instruction immediately before the reti instruction and set the inte flag to 1. to execute the reti instruction following the ei instruction, no interrupt is accepted between ei instruction execution and reti instruction execution. this is because the ei instruction sets the inte flag to 1 after the execution of the subsequent instruction is completed. example load contents of stack pointed to by stack pointer into program counter execute reti instruction load contents of interrupt-dedicated stack into psword increment stack pointer value by one timer 0 interrupt generation timer 1 interrupt generation (held) ei instruction execution timer 0 interrupt generation (held) reti timer 1 interrupt processing ei reti timer 0 interrupt processing single interrupt chapter 14 interrupt functions 160 14.3.3 interrupt accepting timing figure 14-4 shows a timing chart that illustrates how interrupts are accepted. the m pd17134a subseries xecutes one instruction in 16 clocks or in 1 instruction cycle. one instruction cycle consists of four states, m0 to m3, with each state made up of 4 clocks. an interrupt occurs asynchronously in respect to the program operation. the program recognizes the occurrence of the interrupt at the leading edge of state m2. figure 14-4. interrupt accepting timing (when inte = 1, ip = 1) (1/3) (1) if interrupt occurs before m2 of instruction other than movt and ei (2) if skip condition of skip instruction is satisfied in (1) (3) if interrupt occurs after m2 of instruction other than movt and ei m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 skip instruction occurrence of interrupt is recognized. treated as nop int cycle machine cycle instruction irq instruction of vector address m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 instruction other than movt and ei occurrence of interrupt is recognized. int cycle instruction of vector address machine cycle instruction irq m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 instruction other than movt and ei occurrence of interrupt is recognized. instruction other than movt and ei int cycle machine cycle instruction irq instruction of vector address chapter 14 interrupt functions 161 figure 14-4. interrupt accepting timing (when inte = 1, ip = 1) (2/3) (4) if interrupt occurs before m2 of movt instruction (5) if interrupt occurs before m2? of movt instruction (6) if interrupt occurs before m2 of ei instruction (7) if interrupt occurs after m2 of ei instruction m0 m1 m2 m3 m0' m1' m2' m3' m0 m1 m2 m3 m0 m1 movt instruction occurrence of interrupt is recognized. int cycle machine cycle instruction irq instruction of vector address m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 ei instruction occurrence of interrupt is recognized. int cycle machine cycle instruction irq instruction of vector address instruction other than movt and ei m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 ei instruction occurrence of interrupt is recognized. int cycle machine cycle instruction irq instruction of vector address instruction other than movt and ei m0 m1 m2 m3 m0' m1' m2' m3' m0 m1 m2 m3 m0 m1 movt instruction occurrence of interrupt is recognized. int cycle machine cycle instruction irq instruction of vector address chapter 14 interrupt functions 162 figure 14-4. interrupt accepting timing (when inte = 1, ip = 1) (3/3) (8) if interrupt occurs during skip of skip instruction (treated as nop) remarks 1. the int cycle is for preparation of an interrupt. in this cycle, the contents of pc and psword are saved, and irq is cleared. 2. the movt instruction exceptionally requires 2 instruction cycles. 3. the ei instruction is designed so that multiplexed interrupt does not occur when program execution returns from interrupt processing. m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 m2 m3 m0 m1 skip instruction occurrence of interrupt is recognized. treated as nop int cycle machine cycle instruction irq instruction of vector address chapter 14 interrupt functions 163 14.4 multi-interrupt multi-interrupt is a method that executes interrupt processing of other interrupt source b and c during the interrupt processing for an interrupt source a as shown in figure 14-5. nesting level at this time is also called interrupt level. pay attention to the following points when using multi-interrupt. (1) priority of interrupt source (2) limit of interrupt levels by interrupt stack (maximum 3 levels for the m pd17134a subseries) figure 14-5. example of multi-interrupt main processing interrupt processing a interrupt processing b interrupt processing c ei achievement of interrupt a ei (enables multi-interrupt) achievement of interrupt b interrupt disabled enables interrupt in interrupt processing a interrupt disabled reti interrupt enabled achievement of interrupt c reti interrupt enabled enables interrupt in interrupt processing a interrupt disabled reti ei ei ei chapter 14 interrupt functions 164 as shown in figure 14-5, inte flag is cleared automatically and becomes interrupt disable state when interrupt has been achieved. therefore, when executing multi-interrupt processing, execute ei instruction during interrupt processing. caution maximum number of interrupt levels is 3. when achieving interrupt, interrupt stack register and address stack register are consumed by one level. address stack register is consumed by movt instruction and push instruction other than call instruction. pay attention to the nesting level of address stack. 14.5 program example of interrupt ? program example of countermeasure for noise reduction of external interrupt (int pin) this example assumes the case of assigning int pin for key input, etc. when taking into the microcomputer data in kind of switch such as key input processing, it takes some time for the level of input voltage to be stabilized after pushing the key or switch. accordingly, the countermeasures for removing the noise generated by key, etc. should be executed by software. in the following program, after generating external interrupt, the signal from int pin becomes effective after confirming that there is no change in the level of int pin two times in every 100 m s. example waitcnt mem 0.00h ; counter of wait processing chkram mem 0.01h keyon flg 0.01h.3 ; if key turns on (even just once), keyon = 1 chk100u flg 0.01h.0 ; chk100u = 1 only when passing 100 m s during wait loop org 0h br job_init org 5h br int_job job_init: mov waitcnt, #0 ; clears ram and the flag on ram mov chkram, #0 ; initflg not iegmd1, iegmd0 ; rising edge is effective for the interrupt from int pin clr1 irq set1 ip ei main: call 55job call 55job br main . . . . . . . . . . . . . . . chapter 14 interrupt functions 165 int_job: nop ; loop which executes waiting for 100 m s at 8 mhz nop ; 2 m s (1 instruction) 5 instructions 10 times ; (count value at wait) add waitcnt, #01 ; ske waitcnt, #0a ; br int_job ; skf1 int ; check the level of int pin br key_no ; if int pin is high level, interrupt is invalid, and returns ; to main processing skf1 chk100u ; first wait? (chk100u = 0?) br wait_end ; if it is the first time, wait again after setting chk100u. ; in the case of the second time, finish wait processing set1 chk100u ; br int_job wait_end: set1 key_on ; judges that there is key input key_no: clr1 chk100u ; chk100u ? 0 ei reti [memo] 166 chapter 15 ac zero cross detection the int pin is the interrupt signal input pin and timer count clock input pin. it also used as an ac zero cross detector input pin. this pin can be selected by writing 1 in zcross (rf: 1dh bit 0). figure 15-1. block diagram for the ac zero cross detector caution when the ac zero cross detection circuit is used, the current consumption slightly increases (to 15 m a typ.) even in the standby mode. to prevent an increase in the current consumption, clear zcross to 0, and fix the input voltage of the int pin to the high or low level. the zero cross detector consists of a high gain amplifier which uses the self-bias method. it biases the input to the switching point and causes digital displacement in response to slight displacement of int pin input. it detects changes of an ac signal from minus to plus and vice versa. this signal is input through the external coupling capacitor. the signal changes 0 to 1 and vice versa at each displacement point. zcross 00 rf : 1dh internal bus 0 external coupling capacitor ac zero cross detector zero cross detection signal (to int, tm0, btm) ac int 167 chapter 15 ac zero cross detection 168 figure 15-2. zero cross detection signal note the range of the input voltage when the int pin is used as the input pin of the ac zero cross circuit is 1.0 v p-p to 3.0 v p-p . because the ac zero cross circuit does not have a function to reject noise, input a signal from which noise has been eliminated in advance to this circuit. a pulse generated in the zero cross detector can be used as a timer 0 count clock and basic interval timer count clock in the same way as when the pulse does not go through the zero cross detector. the pulse is sent to the interrupt control circuit. interrupt processing starts if an int pin interrupt is enabled. to accept an interrupt, set iegmd0 (rf: 1fh bit 0) and iegmd1 (rf: 1fh bit 1) to select a signal rising edge, falling edge, or both rising and falling edges. v p-p note 0 v ac input waveform ( a ) zero cross detection signal ( b ) chapter 16 standby function 16.1 overview of the standby function the m pd17134a subseries has a standby function to reduce the current consumption. the standby function can be used in two modes which can be selected as the application requires: stop and halt modes. in the stop mode, the system clock is stopped. therefore, the current consumption of the cpu in this mode is only the leakage current. this mode is effective for holding the contents of the data memory without the cpu operating. in the halt mode, oscillation of the system clock continues, but the cpu is stopped because supply of the clock to the cpu is stopped. the current consumption in this mode is greater than in the stop mode. however, operation can be resumed immediately after the halt mode has been released because the system clock is oscillating. in both the stop and halt modes, the contents of the data memory and registers, and the status of the output latch of the output port immediately before the standby mode is set are retained (except stop 0000b). therefore, set the port status to reduce the overall current consumption of the system before setting a standby mode. table 16-1. status in standby mode stop mode halt mode setting instruction stop instruction halt instruction system clock oscillation circuit oscillation stops oscillation continues operating cpu ? operation stops status ram ? retains previous status port ? retains previous status note tm0 ? can operate only when int input is ? can operate selected as count pulse ? stops if system clock is selected (count value is retained) tm1 ? operation stops ? can operate (count value is reset to 0) (count up is also disabled) btm ? operation stops ? can operate (count value is retained) sio ? can operate only when external clock is ? can operate selected as serial clock note a/d ? operation stops note (adcr ? 00h) ? can operate int ? can operate ? can operate note when stop 0000b is executed, these pins are set in the input port mode including when the multiplexed function of the pin is used. cautions 1. be sure to place a nop instruction immediately before the stop or halt instruction. 2. the standby mode is not set if both the interrupt request flag and interrupt enable flag are set and the interrupt is specified as the condition to release the standby mode. 169 chapter 16 standby function 170 16.2 halt mode 16.2.1 setting halt mode the halt mode is set when the halt instruction is executed. operand b 3 b 2 b 1 b 0 of the halt instruction specifies the condition under which the halt mode is released. table 16-2. halt mode release condition format: halt b 3 b 2 b 1 b 0 bit halt mode release condition note 1 b 3 enables release by irq when 1 notes 2, 4 b 2 fixed to 0 b 1 enables forced release by irqtm1 when 1 notes 3, 4 b 2 fixed to 0 notes 1. halt 0000b enables only reset (reset input, power-on/power-down reset). 2. ip must be 1. 3. the halt mode is released regardless of the status of iptm1. 4. even if the halt instruction is executed while irq = 1, the halt instruction is ignored (treated as a nop instruction), and the halt mode is not set. 16.2.2 start address after halt mode is released the address from which program execution is started after the halt mode has been released differs depending on the release condition and interrupt enable condition. table 16-3. start address after halt mode is released release condition start address after halt mode is released reset note 1 address 0 irq note 2 address next to halt instruction in di status interrupt vector in ei status (if two or more irq are set, interrupt vector with highest priority) notes 1. reset input and power-on/power-down reset are valid. 2. ip must be 1 except when the halt mode is forcibly released by irqtm1. chapter 16 standby function 171 figure 16-1. releasing halt mode (a) by reset input (b) by irq (in di status) (c) by irq (in ei status) halt instruction executed tm1 counts up operation mode halt mode system reset status wait operation mode (starts from address 0) wait: wait time until tm1 counts 256 clocks divided by 512 256 512/f cc + a (approx. 65 ms + a , f cc = 2 mhz) a : oscillation growth time (differs depending on resonator) reset operation mode halt mode operation mode irq halt instruction executed halt instruction executed operation mode halt mode operation mode irq interrupt processing accepted chapter 16 standby function 172 16.2.3 halt mode setting conditions (1) forced releasing by irqtm1 setting conditions release by external clock ? timer 0 and timer 1 are used as 16-bit timer (tm0ck1 = 1, tm0ck0 = 1, tm1ck1 = 1, tm1ck0 = 1) ? timer 0 and timer 1 are enabled to operate (tm0en = 1, tm1en = 1) ? interrupt flag of timer 1 is cleared (irqtm1 = 0) release by internal clock ? timer 1 is enabled to operate ? interrupt request flag of timer 1 is cleared (irqtm1 = 0) (2) release by interrupt request flag (irq ) ? peripheral hardware used to release halt mode is enabled to operate in advance. timer 0 operation enabled (tm0en = 1) timer 1 operation enabled (tm1en = 1) timer 0 + timer 1 timer 1 selects count up signal from timer 0 as count pulse (tm1ck1 = 1, tm1ck0 = 1). timer 0 and timer 1 are enabled to operate (tm0en = 1, tm1en = 1) basic interval timer always enabled to operate serial interface serial interface circuit is enabled to operate (siots = 1, sioen = 1) int pin edge selected ? clear the interrupt request flag (irq ) of the peripheral hardware used to release the halt mode to 0. ? set the interrupt enable flag (ip ) of the peripheral hardware used to release the halt mode to 1. caution be sure to include a nop instruction immediately before the halt instruction. by doing so, a time of one instruction is created between the irq manipulation instruction and halt instruction. consequently, clearing irq is correctly reflected on the halt instruction in the case, for example, of the clr1 irq instruction (refer to example 1 below). unless a nop instruction is described immediately before the halt instruction, the clr1 irq instruction is not correctly reflected on the halt instruction, and the halt mode is not set (example 2). chapter 16 standby function 173 example 1. correct program (setting of irq ) clr1 irq nop ; describe nop instruction immediately before halt instruction. ; (clearing of irq is correctly reflected on halt instruction.) halt 1000b ; correctly execute halt instruction (halt mode is set). 2. incorrect program (setting of irq ) clr1 irq ; clearing of irq is not reflected on halt instruction. ; (it is reflected on instruction next to halt instruction.) halt 1000b ; halt instruction is ignored (halt mode is not set). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . chapter 16 standby function 174 16.3 stop mode 16.3.1 setting of stop mode the stop mode is set by executing the stop instruction. the operand b 3 b 2 b 1 b 0 of the stop instruction specifies the condition under which the stop mode is to be released. table 16-4. stop mode release condition format: stop b 3 b 2 b 1 b 0 bit stop mode release condition note 1 b 3 enables release of stop mode by irq when 1 note 2 b 2 fixed to 0 b 1 fixed to 0 b 0 fixed to 0 notes 1. stop 0000b enables only reset (reset input or power-on/power-down reset). the internal circuitry of the microcontroller is initialized to the status immediately after reset when stop 0000b is executed. 2. ip must be 1. the stop mode cannot be released by irqtm1. even if the stop instruction is executed when irq = 1, the stop instruction is ignored (treated as nop), and the stop mode is not set. 16.3.2 start address after stop mode is released the address from which program execution is started after the stop mode has been released differs depending on the release condition and interrupt enable condition. table 16-5. start address after stop mode is released release condition start address after stop mode is released reset note 1 address 0 irq note 2 address next to that of stop instruction in di status interrupt vector in ei status (if two or more irq are set, interrupt vector with highest priority) notes 1. only reset input and power-on/power-down reset are valid. 2. ip must be 1. the stop mode cannot be released by irqtm1. chapter 16 standby function 175 figure 16-2. releasing stop mode (a) releasing stop mode by reset input (b) releasing stop mode by irq (in di status) (c) releasing stop mode by irq (in ei status) stop instruction executed tm1 counts up operation mode stop mode system reset status wait operation mode (starts from address 0) wait: wait time until tm1 counts 256 clocks divided by 512 256 512/f cc + a (approx. 65 ms + a , f cc = 2 mhz) a : oscillation growth time (differs depending on resonator) reset stop instruction executed operation mode stop mode operation mode irq tm1 counts up wait wait: wait time until tm1 counts (n + 1) clocks divided by m (n + 1) m/f cc + a (n and m are values immediately before stop mode is set) a : oscillation growth time (differs depending on resonator) stop instruction executed operation mode stop mode operation mode irq tm1 counts up, interrupt processing accepted wait wait: wait time until tm1 counts (n + 1) clocks divided by m (n + 1) m/f cc + a (n and m are values immediately before stop mode is set) a : oscillation growth time (differs depending on resonator) chapter 16 standby function 176 16.3.3 stop mode setting conditions when stop mode is to be released by irq releasing by irq ? selects edge of signal to be input from int pin (iegmd1, iegmd0). ? sets modulo register value of timer 1 (that creates oscillation stabilization wait time). ? clears interrupt request flag (irq) of int pin to 0. ? sets interrupt enable flag (ip) of int pin to 1. releasing by irqsio ? selects external clock input from sck pin as source clock (siock1 = 0, siock0 = 0). ? enables serial interface to operate (siots = 1). ? sets modulo register value of timer 1 (that sets oscillation stabilization time). ? clears interrupt request flag of serial interface (irqsio) to 0. ? sets interrupt enable flag of serial interface (ipsio) to 1. releasing by irqtm0 ? selects external clock input from int pin as source clock of timer 0 (tm0ck1 = 1, tm0ck0 = 1). ? sets modulo register value of timer 0. ? sets modulo register value and source clock of timer 1 (that creates oscillation stabilization time). ? enables timer 0 to operate (tm0en = 1). ? clears interrupt request flag (irqtm0) to 0 ? sets interrupt enable flag of timer 0 (iptm0) to 1. chapter 16 standby function 177 caution be sure to include a nop instruction before the stop instruction. by doing so, a time of one instruction is created between the irq manipulation instruction and stop instruction. as a result, clearing irq , for example, is correctly reflected on the stop instruction when the irq instruction is executed (refer to example 1 below). unless a nop instruction is described immediately before the stop instruction, the clr1 irq instruction is not reflected on the stop instruction, and the stop mode is not set (example 2). example 1. correct program (setting of irq ) clr1 nop irq ; describe nop instruction immediately before the stop instruction. ; (clearing irq is correctly reflected on the stop instruction.) stop 1000b ; stop instruction is correctly executed (stop mode is set). 2. incorrect program (setting of irq ) clr1 irq ; clearing irq is not reflected on the stop instruction. ; (it is reflected on the instruction next to the stop instruction.) stop 1000b ; the stop instruction is ignored (stop mode is not set). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [memo] 178 chapter 17 reset the m pd17134a subseries is reset in the following four ways. (1) by reset input (2) power-on/power-down reset that resets the microcontroller on power application or when supply voltage drops (3) watchdog timer that resets the microcontroller in case of a program hang-up (4) reset because of overflow/underflow of address stack the power-on/power-down reset function is effective when the supply voltage is 4.5 to 5.5 v. 179 chapter 17 reset 180 17.1 reset function the reset function is used to initialize the device operation. how the device is initialized differs depending on the type of reset effected. table 17-1. hardware status at reset program counter general-purpose data memory system register control register 0000h input 0 undefined undefined 0 undefined 0000h input 0 retains previous status undefined 0 retains previous status 0000h input undefined undefined undefined 0 undefined ? reset input during operation ? internal power-on/ power-down reset during operation ? reset input in standby mode ? internal power-on/ power-down reset in standby mode port sp = 5h, irqtm1 = 1, tm1en = 1, irqbtm = 0, and int = status of int pin at that time. others are 0. refer to chapter 9 register file (rf) . timer 0: 00h, timer 1: undefined ffh undefined (40h if watchdog timer overflows) undefined 00h 00h 00h timer 0 and timer 1 count register ffh ffh modulo register counter of basic interval timer retains previous status shift register of serial interface (siosfr) data register of a/d converter (adcr) undefined 00h 00h sp = 5h, int = status of int pin at that time. others retain previous status. undefined undefined ? overflow of watchdog timer ? overflow and underflow of stack i/o mode output latch other than dbf dbf other than wr wr hardware reset method chapter 17 reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 181 figure 17-1. reset block configuration 17.2 resetting operation when system reset is caused by the reset pin is shown in the figure below. if the reset pin is set from low to high, system clock oscillation starts and an oscillation stabilization wait occurs with the timer 1. program execution starts from address 0000h. if power-on reset is used, the reset signals shown in figure 17-2 are internally generated. operation is the same as that when reset is caused externally by the reset pin. at watchdog timer overflow reset or stack overflow and underflow reset, oscillation stabilization wait time (wait) does not occur. operation starts from address 0000h after initial statuses are internally set. figure 17-2. reset operation note this is oscillation stabilization wait time. operating mode is set when timer 1 counts system clocks (f cc ) 512 256 counts approx. 65 ms at f cc = 2 mhz). rf : 10h internal bus 0 0 0 pdresen clear power-down reset circuit power-on reset circuit internal reset signal mask option reset v dd operating mode reset wait note operating mode reset tm1en tm1res chapter 17 reset 182 17.3 power-on/power-down reset function the m pd17134a subseries is provided with two reset functions to prevent malfunctions from occurring in the microcontroller. they are the power-on reset function and power-down reset function. the power-on reset function resets the microcontroller when it detects that power was turned on. the power-down reset function resets the microcontroller when it detects drops in the power voltage. these functions are implemented by the power monitoring circuit whose operating voltage has a different range than the logic circuits in the microcontroller and the oscillation circuit (which stops oscillation at reset to put the microcontroller in a temporary stop state). conditions required to enable these functions and their operations will be described next. caution when designing an application circuit that calls for high reliability, do not depend on the internal power-on/power-down reset function only. make sure that an external reset signal is input. 17.3.1 conditions required to enable the power-on reset function this function is effective when used together with the power-down reset function. the following conditions are required to validate the power-on reset function: (1) the power voltage must be within 4.5 to 5.5 v during normal operation, including the standby state. (2) the frequency of the system clock oscillator must be 400 khz to 4 mhz. note (3) the power-down reset function must be enabled during normal operation, including the standby state. (4) the power voltage must rise from 0 v to the specified voltage. (5) the time it takes for the power voltage to rise from 0 to 2.7 v must be shorter than the oscillation stabilization wait time (system clock f cc = 512 256 counts, about 65 ms, at f cc = 2 mhz) counted in timer 1. note applies to the m pd17135a, 17137a, and 17p137a. when the m pd17134a, 17136a, or 17p136a is used, f cc = 400 khz to 2 mhz. cautions 1. if the above conditions are not satisfied, the power-on reset function will not operate effectively. in this case, an external reset circuit needs to be added. 2. in the standby state, even if the power-down reset function operates normally, general- purpose data memory (except dbf) retains data up to v dd = 2.7 v. if, however, data is changed due to an external error, the data in memory is not guaranteed. chapter 17 reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 183 17.3.2 power-on reset function and operation the power-on reset function resets the microcontroller when it detects that power was turned on in the hardware, regardless of the software state. the power-on reset circuit operates under a lower voltage than the other internal circuits. it initializes the microcontroller regardless whether the oscillation circuit is operating. when the reset is terminated, timer 1 counts the number of oscillation pulses sent from the oscillator until it reaches the specified value. within this period, oscillation becomes stable and the power voltage applied to the microcontroller enters the range (v dd = 2.7 to 5.5 v at 400 khz to 4 mhz) in which the microcontroller is guaranteed to operate. when this period elapses, the microcontroller enters normal operation mode. figure 17-3 shows an example of the power-on reset operation. functions of the power-on reset (1) this circuit always monitors the voltage applied to the v dd pin. (2) this circuit resets the internal circuit of the microcomputer, regardless of whether the oscillator circuit operates or not, when the supply voltage rises, until the voltage reaches the power-on reset clear voltage (v dd = 1.5 v typ.). note (3) this circuit stops oscillation during the reset operation. (4) when reset is released, timer 1 counts oscillation pulses. the microcontroller waits until oscillation becomes stable and the power voltage becomes v dd = 2.7 v or higher. note the internal circuit of the microcontroller is not reset until the supply voltage reaches the level at which the internal circuit can operate (i.e., internal reset signal can be accepted). chapter 17 reset 184 figure 17-3. example of the power-on reset operation notes 1. during the operation-undefined period, not all of the operations specified for the m pd17134a subseries are guaranteed. the power-on reset operation is guaranteed in this period. 2. the operation-guaranteed period refers to the time in which all the operations specified for the m pd17134a subseries are guaranteed. 3. an operation stop state refers to the state in which all of the functions of the microcontroller are stopped. v dd (v) 5.0 2.7 a b 0 a : voltage at which oscillation starts b : voltage at which the power-on reset operation terminates v dd reset note 4 gnd m pd17134a subseries time (t) oscillating timer 1 finishes counting state of oscillation oscillation start oscillation stop undefined period note 1 guaranteed period note 2 operation stop note 3 power-on reset termination operating mode period in which the microcon- troller is guar- anteed to operate power-on reset signal operation state of the micro- controller waiting until oscillation becomes stable chapter 17 reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 185 17.3.3 condition required for use of the power-down reset function the power-down reset function can be enabled or disabled using software. the following condition is required to use this function: ? the power voltage must be within 4.5 to 5.5 v during normal operation, including the standby state. ? the frequency of the system clock oscillator must be 400 khz to 4 mhz. caution when the microcontroller is used with a power voltage of 2.7 to 4.5 v, add an external reset circuit instead of using the internal power-down reset circuit. if the internal power-down reset circuit is used with a power voltage of 2.7 to 4.5 v, reset operation may not terminate. 17.3.4 power-down reset function and operation this function is enabled by setting the power-down reset enable flag (pdresen) using software. when this function detects a power voltage drop, it issues the reset signal to the microcontroller. it then initializes the microcontroller. stopping oscillation during reset prevents the power voltage in the microcontroller from fluctuating out of control. when the specified power voltage recovers and the power-down reset operation is terminated, the microcontroller waits the time required for stable oscillation using the timer. the microcontroller then enters normal operation (starts from address 0). figure 17-4 shows an example of the power-down operation. figure 17-5 shows an example of reset operation during the period from power-down reset to power recovery. functions of the power-down reset (1) this circuit always monitors the voltage applied to the v dd pin. (2) when this circuit detects a power voltage drop, it issues a reset signal to the other parts of the microcontroller. it continues to send this reset signal until the power voltage recovers or all the functions in the microcontroller stop. (3) this circuit stops oscillation during the reset operation to prevent software crashes. when the power voltage recovers to the low-voltage detection level (3.5 v typ., 4.5 v max.) before the power- down reset function stops, the microcontroller waits the time required for stable oscillation using timer 1, then enters normal operation mode. (4) when the power voltage recovers from 0 v, the power-on reset function has priority. (5) after the power-down reset function stops and the power voltage recovers before it reaches 0 v, the microcontroller waits using timer 1 until oscillation becomes stable and the power voltage (v dd ) reaches 2.7 v. the microcontroller then enters normal operation mode. chapter 17 reset 186 figure 17-4. example of the power-down reset operation note in the operation-undefined period, not all the operations specified for the m pd17134a subseries are guaranteed. the power-down reset operation, which continues to issue a reset signal until all the functions in the microcontroller stop, is guaranteed in this period. maximum voltage detected by the power-down reset function: 4.5 v typical voltage detected by the power-down reset function: 3.5 v voltage at which the power-down reset function terminates = power-on reset voltage (b): c reset gnd v dd m pd17134a subseries time (t) state of oscillation guaranteed period undefined period note operating mode power-down reset period in which the microcon- troller is guar- anteed to operate power-down reset signal operation state of the micro- controller oscillating oscillation stop power-on reset signal reset state 5.0 3.5 2.7 c 0 4.5 v dd (v) chapter 17 reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 187 figure 17-5. example of reset operation during the period from power-down reset to power recovery note in the operation-undefined period, not all the operations specified for the m pd17134a subseries are guaranteed. the power-down reset operation, which continues to issue the reset signal until all the functions in the microcontroller stop, is guaranteed in this period. state of oscillation period in which the microcon- troller is guar- anteed to operate power-down reset signal power-on reset signal operation state of the micro- controller oscillating operating mode reset state power-down reset waiting until oscillation becomes stable operating mode timer 1 finishes counting oscillating 5.0 4.5 3.5 2.7 c 0 maximum voltage detected by the power-down reset function: 4.5 v typical voltage detected by the power-down reset function: 3.5 v voltage at which the power-down reset function terminates = power-on reset voltage (b): c time (t) guaranteed period undefined period note (v) oscillation stop v dd reset gnd v dd m pd17134a subseries guaranteed period [memo] 188 chapter 18 one-time prom writing/verifying the on-chip program memories of the m pd17p136a and 17p137a are is a 2048 16-bit one-time prom. pins listed in table 18-1 are used for one-time prom writing/verifying. the address is updated by the clock signal input from the clk pin. caution pib 0 /v pp pin is used as v pp pin in program writing/verifying mode. therefore, there is a possibility of overrunning of the microcontroller when higher voltage than v dd + 0.3 v is applied to pib 0 /v pp pin in normal operation mode. pay careful attention to pin protection. table 18-1. pins used for writing/verifying program memory pin function v pp applies program voltage. apply +12.5 v to this pin. v dd power supply pin. apply +6 v to this pin. reset system reset input pin. used for initializing all states before setting program memory writing/verifying mode. clk clock input for updating address. updates program memory address by inputting four pulses. md 0 -md 3 select operation mode. d 0 -d 7 8-bit data i/o pins. 18.1 differences between mask rom version and one-time prom model the m pd17p136a and 17p137a are microcontrollers replacing the program memory of the on-chip mask rom version m pd17136a and 17137a to one-time prom. table 18-2 shows the differences between mask rom version and one-time prom version. differences between each product are only its program memory, program size, address register size, and whether it can specify mask option or not. the cpu function and internal peripheral hardware of each product are the same. therefore, the m pd17p136a can be used for evaluating program of the m pd17134a/17136a in system development. also, the m pd17p137a can be used for evaluating the m pd17135a/17137a in the same way. 189 chapter 18 one-time prom writing/verifying 190 table 18-2. differences between mask rom version and one-time prom version item m pd17134a/17135a m pd17136a/17137a m pd17p136a/17p137a rom mask rom one-time prom 1024 16 bits 2048 16 bits (0000h to 03ffh) (0000h to 07ffh) program counter address register 10 bits 11 bits address stack register p0d, p1a, and p1b pins and mask option not available pull-up resistor of reset pin v pp pin and operating mode select not available provided pin quality grade standard standard special [(a), (a1)] caution the prom model is highly compatible with the mask rom model in terms of functions but its internal rom circuit and electrical characteristics are partially different from those of the mask rom model. to replace the prom model with the mask rom model, thoroughly evaluate the application by using a sample of the mask rom model. 18.2 operation mode when program memory is written/verified the m pd17p136a and 17p137a enter a program memory write/verify mode when they have been reset for a fixed time (v dd = 5 v, reset = 0 v) and then +6 v is applied to the v dd pin and +12.5 v to the v pp pin. in this mdoe, the operation modes shown in the table below can be selected depending on the setting of the md 0 through md 3 pins. connect v adc directly to v dd . connect all the other pins to gnd via pull-down resistor. table 18-3. setting operation modes setting operation mode operation mode v pp v dd md 0 md 1 md 2 md 3 h l h l program memory address 0 clear +12.5 v +6 v l h h h write mode l l h h verify mode h h h program inhibit mode remark : dont care (l or h) chapter 18 one-time prom writing/verifying 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 191 18.3 writing procedure of program memory the program memory can be written at high speeds in the following procedure. (1) pull down the unused pins to gnd. make the clk pin low. (2) apply 5 v to the v dd pin. make v pp pin and reset pin low. (3) wait for 10 m s. then, apply 5 v to reset pin. (4) set the program memory address 0 clear mode using mode selector pins. (5) apply 6 v to v dd and reset, and 12.5 v to vpp. (6) set the program inhibit mode. (7) write data in mode for 1 ms writing. (8) set the program inhibit mode. (9) set the verify mode. if the program has been correctly written, proceed to (10). if not, repeat (7) through (9). (10) additional writing of (number of times ( ) the program has been written in (7) through (9)) 1 ms. (11) set the program inhibit mode. (12) input four pulses to the clk pin to update the program memory address by one. (13) repeat (7) through (12) until the last address is programmed. (14) set the program memory address 0 clear mode. (15) change the voltage of v dd and v pp pins to 5 v. (16) turn off the power. figure 18-1 shows the procedures of (2) through (12). figure 18-1. procedure of program memory writing address increment additional writing verify write repeat times reset v dd +1 v dd gnd v dd +1 v dd gnd v pp v dd gnd clk v dd reset v pp d 0 - d 7 md 0 md 1 md 2 md 3 hi-z hi-z hi-z hi-z input data input data output data chapter 18 one-time prom writing/verifying 192 18.4 reading procedure of program memory (1) connect v adc directly to v dd , and all the other pins to gnd via pull-down resistor. make the clk pin low. (2) apply 5 v to the v dd pin. make v pp pin and reset pin low. (3) wait for 10 m s. then, apply 5 v to reset pin. (4) set the program memory address 0 clear mode using mode selector pins. (5) apply 6 v to v dd and reset and 12.5 v to v pp . (6) set mode selector pins to the program inhibit mode. (7) set the verify mode. when clock pulses are input to the clk pin, data for each address can be sequentially output with four clocks as one cycle. (8) set the program inhibit mode. (9) set the program memory address 0 clear mode. (10) change the voltage of v dd and v pp pins to 5 v. (11) turn off the power. figure 18-2 shows the program reading procedure (2) through (9). figure 18-2. procedure of program memory reading reset v dd +1 v dd gnd v dd +1 v dd gnd v pp v dd gnd clk v dd reset v pp d 0 - d 7 md 0 md 1 md 2 md 3 hi-z hi-z output data output data l chapter 19 instruction set 19.1 overview of the instruction set hex 0 1 2 3 4 5 6 8 9 a b c d e f bin 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 add r, m sub r, m addc r, m subc r, m and r, m xor r, m or r, m inc ar inc ix movt dbf, @ar br @ar call @ar ret retsk ei di reti push ar pop ar get dbf, p put p, dbf peek wr, rf poke rf, wr rorc r stop s halt h nop ld r, m ske m, #n4 mov @r, m skne m, #n4 br addr add m, #n4 sub m, #n4 addc m, #n4 subc m, #n4 and m, #n4 xor m, #n4 or m, #n4 st m, r skge m, #n4 mov m, @r sklt m, #n4 call addr mov m, #n4 skt m, #n skf m, #n 0 1 1 1 7 0 1 b 14 -b 11 b 15 193 chapter 19 instruction set 194 19.2 legend ar : address register asr : address stack register indicated by stack pointer addr : program memory address (11 bits) bank : bank register cmp : compare register cy : carry flag dbf : data buffer h : halt release condition intef : interrupt enable flag intr : register saved automatically to interrupt stack intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address indicated by m r and m c m r : data memory row address (high-order) m c : data memory column address (low-order) n : bit position (4 bits) n4 : immediate data (4 bits) pc :program counter p : peripheral address p h : peripheral address (high-order 3 bits) p l : peripheral address (low-order 4 bits) r : general register column address rf : register file address rf r : register file row address (high-order 3 bits) rf c : register file column address (low-order 4 bits) sp :stack pointer s : stop release condition wr : window register ( 5 ) : contents addressed by chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 195 19.3 list of the instruction set machine code group mnemonic operand operation op code operand add add r, m (r) ? (r) + (m) 00000 m r m c r m, #n4 (m) ? (m) + n4 10000 m r m c n4 addc r, m (r) ? (r) + (m) + cy 00010 m r m c r m, #n4 (m) ? (m) + n4 + cy 10010 m r m c n4 inc ar ar ? ar + 1 00111 000 1001 0000 ix ix ? ix + 1 00111 000 1000 0000 subtract sub r, m (r) ? (r) C (m) 00001 m r m c r m, #n4 (m) ? (m) C n4 10001 m r m c n4 subc r, m (r) ? (r) C (m) C cy 00011 m r m c r m, #n4 (m) ? (m) C n4 C cy 10011 m r m c n4 logical or r, m (r) ? (r) v (m) 00110 m r m c r operation m, #n4 (m) ? (m) v n4 10110 m r m c n4 and r, m (r) ? (r) (m) 00100 m r m c r m, #n4 (m) ? (m) n4 10100 m r m c n4 xor r, m (r) ? (r) v (m) 00101 m r m c r m, #n4 (m) ? (m) v n4 10101 m r m c n4 judge skt m, #n cmp ? 0, if (m) n = n, then skip 11110 m r m c n skf m, #n cmp ? 0, if (m) n = 0, then skip 11111 m r m c n compare ske m, #n4 (m) Cn4, skip if zero 01001 m r m c n4 skne m, #n4 (m) Cn4, skip if not zero 01011 m r m c n4 skge m, #n4 (m) Cn4, skip if not borrow 11001 m r m c n4 sklt m, #n4 (m) Cn4, skip if borrow 11011 m r m c n4 rotate rorc r cy ? (r) b3 ? (r) b2 ? (r) b1 ? (r) b0 00111 000 0111 r transfer ld r, m (r) ? (m) 01000 m r m c r st m, r (m) ? (r) 11000 m r m c r mov @r, m if mpe = 1: (mp, (r) ? (m) 01010 m r m c r if mpe = 0: (bank, m r , (r)) ? (m) m, @r if mpe = 1: (m) ? (mp, (r)) 11010 m r m c r if mpe = 0: (m) ? (bank, m r , (r)) m, #n4 (m) ? n4 11101 m r m c n4 movt dbf, @ar sp ? sp C1, asr ? pc, pc ? ar, 00111 000 0001 0000 dbf ? (pc), pc ? asr, sp ? sp +1 v v v v chapter 19 instruction set 196 machine code group mnemonic operand operation op code operand transfer push ar sp ? sp C1, asr ? ar 00111 000 1101 0000 pop ar ar ? asr, sp ? sp+1 00111 000 1100 0000 peek wr, rf wr ? (rf) 00111 rf r 0011 rf c poke rf, wr (rf) ? wr 00111 rf r 0010 rf c get dbf, p dbf ? (p) 00111 p h 1011 p l put p, dbf (p) ? dbf 00111 p h 1010 p l branch br addr pc ? addr 01100 addr @ar pc ? ar 00111 000 0100 0000 sub- call addr sp ? sp C1, asr ? pc, pc ? addr 11100 addr routine @ar sp ? sp C1, asr ? pc, pc ? ar 00111 000 0101 0000 ret pc ? asr, sp ? sp +1 00111 000 1110 0000 retsk pc ? asr, sp ? sp +1 and skip 00111 001 1110 0000 reti pc ? asr, intr ? intsk, sp ? sp +1 00111 100 1110 0000 interrupt ei intef ? 1 00111 000 1111 0000 di intef ? 0 00111 001 1111 0000 others stop s stop 00111 010 1111 s halt h halt 00111 011 1111 h nop no operation 00111 100 1111 0000 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 197 19.4 assembler (as17k) embedded macro instructions legend flag n : flg type symbol < > : can be omitted mnemonic operand operation n embedded sktn flag 1, ...flag n if (flag 1) to (flag n) = all 1 then skip 1 n 4 macro skfn flag 1, ...flag n if (flag 1) to (flag n) = all 0, then skip 1 n 4 setn flag 1, ...flag n (flag 1) to (flag n) ? 11 n 4 clrn flag 1, ...flag n (flag 1) to (flag n) ? 01 n 4 notn flag 1, ...flag n if (flag n) = 0, then (flag n) ? 11 n 4 if (flag n) = 1, then (flag n) ? 0 initflg chapter 19 instruction set 198 19.5 instructions 19.5.1 addition instructions (1) add r, m add data memory to general register <1> op code <2> function when cmp = 0, (r) ? (r) + (m) adds the data memory contents to the general register contents, and stores the result in general register. when cmp = 1, (r) + (m) the result is not stored in the register. carry flag cy and zero flag z are changed, according to the result. sets carry flag cy, if a carry occurs as a result of the addition. resets the carry flag, if no carry occurs. if the addition result is other than zero, zero flag z is reset, regardless of compare flag cmp. if the result is zero with the compare flag reset (cmp = 0), the zero flag z is set. if the result is zero with the compare flag set (cmp = 1), the zero flag z is not changed. addition can be executed in binary 4 bits or bcd. the bcd flag for the psword specifies what kind of addition is to be executed. <3> example 1 to add the address 0.2fh contents to the address 0.03h contents, when row address 0 (0.00hC0.0fh) in bank 0 is specified as the general register (rph = 0, rpl = 0), and to store the result in address 0.03h: (0.03h) ? (0.03h) + (0.2fh) mem003 mem 0.03h mem02f mem 0.2fh mov bank, #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 add mem003, mem02f 00000 m r m c r 10 87 43 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 199 example 2 to add the address 0.2fh contents to the address 0.23h contents, when row address 2 (0.20hC0.2fh) in bank 0 is specified as the general register (rph = 0, rpl = 4), and store the result in address 0.23h: (0.23h) ? (0.23h) + (0.2fh) mem023 mem 0.23h mem02f mem 0.2fh mov bank, #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 note mov rpl, #04h ; general register row address 2 add mem023, mem02f rp (general register pointer) is assigned in the system register, as shown above. therefore, to set bank 0 and row address 2 in a general register, 00h must be stored in rph and 04h, in rpl. in this case, the subsequent arithmetic operation is executed in binary 4-bit operation, because the bcd flag is reset. example 3 to add the address 0.6fh contents to the address 0.03h contents and store the result in address 0.3h. at this time, data memory address 0.6fh can be specified, by selecting data memory address 2fh, if ixe = 1, ixh = 0, ixm = 4, and ixl = 0, i.e., ix = 0.40h. (0.03h) ? (0.03h) + (0.6fh) address obtained as result of oring index register contents, 0.40h, and data memory address 0.2fh mem003 mem 0.03h mem02f mem 0.2fh mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 mov ixh, #00h ; ix ? 00001000000b mov ixm, #04h ; mov ixl, #00h ; set1 ixe ; ixe flag ? 1 add mem003, mem02f ; ix 00001000000b (0.40h) ; bank operand or ) 00000101111b (0.2fh) ; specified address 00001101111b (0.6fh) rp rph rpl register bit data b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b c d bank row address 000 note chapter 19 instruction set 200 example 4 to add the address 0.3fh contents to the address 0.03h contents and store the result in address 0.03h. at this time, data memory address 2.3fh can be specified by specifying data memory address 2fh, if ixe = 1, ixh = 0, ixm = 1, and ixl = 0, i.e., ix = 0.10h. (0.03h) ? (0.03h) + (0.3fh) address obtained as result of oring index register contents, 0.10h, and data memory address 0.2fh mem003 mem 0.03h mem02f mem 0.2fh mov bank, #00h mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 mov ixh, #00h ; ix ? 00000010000b (0.10h) note mov ixm, #01h mov ixl, #00h set1 ixe ; ixe flag ? 1 add mem003, mem02f ; ix 00000010000b (0.10h) ; bank operand or ) 00000101111b (0.2fh) ; specified address 00100111111b (0.3fh) ix (index register) is assigned in the system register, as shown above, therefore, to specify ix = 0.10h, 00h must be stored in ixh. 01h in ixm, and 00h in ixl. in this case, mp (memory pointer) for general register indirect transfer is invalid, because the mpe flag (memory pointer enable) is reset. ix ixh ixm register bit data b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 p00 b 2 b 1 b 0 b 3 ixl 0 m e bank row address column address note chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 201 <4> caution the first operand for the add r, m instruction is a column address. therefore, if the instruction is described as follows, the column address for the general register is 03h: mem013 mem 0.13h mem02f mem 0.2fh mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 add mem013, mem02f indicates the general register column address. the low-order 4 bits (in this case, 03h) are valid when cmp flag = 1, the addition result is not stored. when bcd flag = 1, the decimal addition result is stored. (2) add m, #n4 add immediate data to data memory <1> op code <2> function when cmp = 0, (m) ? (m) + n4 adds immediate data to the data memory contents, and stores the result in data memory. when cmp = 1, (m) + n4 the result is not stored in the data memory. carry flag cy and zero flag z are changed, according to the result. sets carry flag cy, if a carry occurs as a result of the addition; resets the carry flag if no carry occurs. if the addition result is other than zero, zero flag z is reset, regardless of compare flag cmp. if the result is zero with the compare flag reset (cmp = 0), the zero flag z is set. if the result is zero with the compare flag set (cmp = 1), the zero flag z is not changed. addition can be executed in binary 4 bits or bcd. the bcd flag for the psword specifies which kind of addition is to be executed. 10000 m r m c n4 10 87 43 0 chapter 19 instruction set 202 <3> example 1 to add 5 to the address 0.2fh contents, and store the result in address 0.2fh: (0.2fh) ? (0.2fh) + 5 mem02f mem 0.2fh add mem02f, #05h example 2 to add 5 to the address 0.6fh contents and store the result in address 0.6fh. at this time, data memory address 0.6fh can be specified by selecting data memory address 2fh, if ixe = 1, ixh = 0, ixm = 4, and ixl = 0, i.e., ix = 0.40h. (0.6fh) ? (0.6fh) + 05h address obtained as result of oring index register contents, 0.40h, and data memory address 0.2fh mem02f mem 0.2fh mov bank, #00h ; data memory bank 0 mov ixh, #00h ; ix ? 00001000000b (0.40h) mov ixm, #04h mov ixl, #00h set1 ixe ; ixe flag ? 1 add mem02f, #05h ; ix 00001000000b (0.40h) ; bank operand or ) 00000101111b (0.2fh) ; specified address 00001101111b (0.6fh) example 3 to add 5 to the address 0.2fh contents and store the result in address 0.2fh. at this time, data memory address 0.2fh can be specified by selecting data memory address 2fh, if ixe = 1, ixh = 0, ixm = 0, and ixl = 0, i.e., ix = 0.00h. (0.2fh) ? (0.2fh) + 05h address obtained as result of oring index register contents, 0.00h, and data memory address 0.2fh mem02f mem 0.2fh mov bank, #00h ; data memory bank 0 mov ixh, #00h ; ix ? 00000000000b mov ixm, #00h mov ixl, #00h set1 ixe ; ixe flag ? 1 add mem02f, #05h ; ix 00000000000b (0.00h) ; bank operand or ) 00000101111b (0.2fh) ; specified address 00000101111b (0.2fh) <4> caution when the cmp flag = 1, the addition result is not stored. when the bcd flag = 1, the decimal addition result is stored. chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 203 (3) addc r, m add data memory to general register with carry flag <1> op code <2> function when cmp = 0, (r) ? (r) + (m) + cy adds the data memory contents to the general register contents with carry flag cy, and stores the result in general register. when cmp = 1, (r) + (m) + cy the result is not stored in the register. carry flag cy and zero flag z are changed according to the result. by using this addc instruction, one or more nibbles can be easily added. sets carry flag cy, if a carry occurs as a result of the addition; resets the carry flag if no carry occurs. if the addition result is other than zero, zero flag z is reset, regardless of compare flag cmp. if the result is zero with the compare flag reset (cmp = 0), the zero flag z is set. if the result is zero with the compare flag set (cmp = 1), the zero flag z is not changed. addition can be executed in binary 4 bits or bcd. the bcd flag for psword specifies which kind of addition is to be executed. <3> example 1 to add the 12-bit contents for addresses 0.0dh through 0.0fh to the 12-bit contents for addresses 0.2dh through 0.2fh, and store the result in the 12-bit contents for address 0.0dh to 0.0fh, when row address 0 (0.00hC0.0fh) of bank 0 is specified as a general register: (0.0fh) ? ( 0.0fh) + (0.2fh) (0.0eh) ? ( 0.0eh) + (0.2eh) + cy (0.0dh) ? ( 0.0dh) + (0.2dh) + cy mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mem02d mem 0.2dh mem02e mem 0.2eh mem02f mem 0.2fh mov bank, #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 add mem00f, mem02f ; low-order nibble addc mem00e, mem02e addc mem00d, mem02d ; high-order nibble 00010 m r m c r 10 87 43 0 chapter 19 instruction set 204 example 2 to shift the 12-bit contents for addresses 0.2dh through 0.2fh 1 bit to the left, when row address 2 in bank 0 (0.20hC0.2fh) is specified as a general register: mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mem02d mem 0.2dh mem02e mem 0.2eh mem02f mem 0.2fh mov rph, #00h ; general register bank 0 mov rpl, #04h ; general register row address 2 mov bank, #00h ; data memory bank 0 addc mem00f, mem02f addc mem00e, mem02e addc mem00d, mem02d example 3 to add the address 0.0fh contents to the addresses 0.40h through 0.4fh contents, and store the result in address 0.0fh: (0.0fh) ? (0.0fh) + (0.40h) + (0.41h) + ... + (0.4fh) mem00f mem 0.0fh mem000 mem 0.00h mov bank, #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 mov ixh, #00h ; ix ? 00001000000b (0.40h) mov ixm, #04h mov ixl, #00h loop1: set1 ixe ; ixe flag ? 1 add mem00f, mem000 clr1 ixe ; ixe flag ? 0 inc ix ; ix ? ix + 1 ske ixl, #0 jmp loop1 cy (carry flag) bank 0 address 0dh bank 0 address 0eh bank 0 address 0fh cy (carry flag) chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 205 example 4 to add the 12-bit contents for addresses 0.40h through 0.42h to the 12-bit contents for addresses 0.0dh through 0.0fh, and store the result in 12-bit contents for addresses 0.0dh through 0.0fh: (0.0dh) ? (0.0dh) + (0.40h) (0.0eh) ? (0.0eh) + (0.41h) + cy (0.0fh) ? (0.0fh) + (0.42h) + cy mem000 mem 0.00h mem001 mem 0.01h mem002 mem 0.02h mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mov bank, #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 mov ixh, #00h ; ix 00001000000 (0.40h) mov ixm, #04h mov ixl, #00h set1 ixe ; ixe flag ? 1 add mem00d, mem000 ; (0.0dh) ? (0.0dh) + (0.40h) ; low-order nibble addc mem00e, mem001 ; (0.0eh) ? (0.0eh) + (0.41h) addc mem00f, mem002 ; (0.0fh) ? (0.0fh) + (0.42h) ; high-order nibble (4) addc m, #n4 add immediate data to data memory with carry flag <1> op code <2> function when cmp = 0, (m) ? (m) + n4 + cy adds immediate data to the data memory contents with carry flag (cy), and stores the result in data memory. when cmp = 1, (m) + n4 + cy the result is not stored in the data memory, and carry flag cy and zero flag z are changed, according to the result. sets carry flag cy, if a carry occurs as a result of the addition. resets the carry flag, if no carry occurs. if the addition result is other than zero, zero flag z is reset, regardless of compare flag cmp. if the result is zero with the compare flag reset (cmp = 0), the zero flag z is set. if the result is zero with the compare flag set (cmp = 1), the zero flag z is not changed. addition can be executed in binary or bcd. the bcd flag for psword specifies which kind of addition is to be executed. 10010 m r m c n4 10 87 43 0 chapter 19 instruction set 206 <3> example 1 to add 5 to the 12-bit contents for addresses 0.0dh through 0.0fh, and store the result in addresses 0.0dh through 0.0fh; (0.0fh) ? (0.0fh) + 05h (0.0eh) ? (0.0eh) + cy (0.0dh) ? (0.0dh) + cy mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mov bank, #00h ; data memory bank 0 add mem00f, #05h addc mem00e, #00h addc mem00d, #00h example 2 to add 5 to the 12-bit contents for addresses 0.4dh through 0.4fh and store the result in addresses 0.4dh through 0.4fh: (0.4fh) ? (0.4fh) + 05h (0.4eh) ? (0.4eh) + cy (0.4dh) ? (0.4dh) + cy mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mov bank, #00h ; data memory bank 0 mov ixh, #00h ; ix ? 00001000000b (0.40h) mov ixm, #04h mov ixl, #00h set1 ixe ; ixe flag ? 1 add mem00f, #5 ; (0.4fh) ? (0.4fh) + 5h addc mem00e, #0 ; (0.4eh) ? (0.4eh) + cy addc mem00d, #0 ; (0.4dh) ? (0.4dh) + cy (5) inc ar increment address register <1> op code <2> function ar ? ar + 1 increments the address register ar contents. 00111 000 1001 0000 10 87 43 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 207 . . . . . . . . <3> example 1 to add 1 to the 16-bit contents for ar3 through ar0 (address registers) in the system register and store the result in ar3 through ar0: ar0 ? ar0 + 1 ar1 ? ar1 + cy ar2 ? ar2 + cy ar3 ? ar3 + cy inc ar this program can be rewritten as follows, with addition instructions: add ar0, #01h addc ar1, #00h addc ar2, #00h addc ar3, #00h example 2 to transfer table data, 16 bits (1 address) at a time, to dbf (data buffer), using the table reference instruction (for details, refer to 10.2.3 table reference ): ; address table data org 10h dw 0f3ffh dw 0a123h dw 0fff1h dw 0fff5h dw 0ff11h mov ar3, #0h ; table data address mov ar2, #0h ; 0010h in address register mov ar1, #1h ; mov ar0, #0h loop: movt dbf, @ar ; reads table data to dbf : : : ; table data reference processing : inc ar ; increments address register by 1 br loop <4> caution the numbers of bits, for address registers ar3 through ar0, differ, depending on the microcontroller model to be used. ? m pd17134a/17135a : 10 bits ? m pd17136a/17137a/17p136a/17p137a : 11 bits chapter 19 instruction set 208 (6) inc ix increment index register <1> op code <2> function ix ? ix + 1 increments the index register ix contents. <3> example 1 to add 1 to the 12-bit contents for ixh, ixm, and ixl (index registers) in the system register and store the result in ixh, ixm, and ixl; ixl ? ixl + 1 ixm ? ixm + cy ixh ? ixh + cy inc ix this program can be rewritten as follows, with addition instructions: add ixl, #01h addc ixm, #00h addc ixh, #00h example 2 to clear all the contents for data memory addresses 0.00h through 0.73h, using the index register: mem000 mem0.00h mov ixh, #00h ; sets index register contents in 00h in bank 0 mov ixm, #00h ; mov ixl, #00h ram clear: set1 ixe ; ixe flag ? 1 mov mem000, #00h ; writes 0 to data memory indicated by index register clr1 ixe ; ixe flag ? 0 inc ix set2 cmp, z ; cmp flag ? 1, z flag ? 1 sub ixl, #03h ; checks whether index register contents subc ixm, #07h ; are 73h in bank 0 subc ixh, #00h ; skt1 z ; loops until contents of index register becomes br ram clear ; 73h of bank 0 00111 000 1000 0000 10 87 43 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 209 19.5.2 subtraction instructions (1) sub r, m subtract data memory from general register <1> op code <2> function when cmp = 0, (r) ? (r) C (m) subtracts the data memory contents from the general register contents, and stores the result in general register. when cmp = 1, (r) C (m) the result is not stored in the register. carry flag cy and zero flag z are changed, according to the result. sets carry flag cy, if a borrow occurs as a result of the subtraction. resets the carry flag, if no borrow occurs. if the subtraction result is other than zero, zero flag z is reset, regardless of compare flag cmp. if the result is zero with the compare flag reset (cmp = 0), the zero flag z is set. if the result is zero with the compare flag set (cmp = 1), the zero flag z is not changed. subtraction can be executed in binary 4 bits or bcd. the bcd flag for psword specifies which kind of subtraction is to be executed. <3> example 1 to subtract the address 0.2fh contents from the address 0.03h contents, store the result in address 0.03h, when row address 0 (0.00hC0.0fh) in bank 0 is specified as a general register (rph = 0, rpl = 0): (0.03h) ? (0.03h) + (0.2fh) mem003 mem 0.03h mem02f mem 0.2fh sub mem003, mem02f example 2 to subtract the address 0.2fh contents from the address 0.23h contents, when row address 2 (0.20hC 0.2fh) in bank 0 is specified as the general register (rph = 0, rpl = 4), and store the result in address 0.23h: (0.23h) ? (0.23h) C (0.2fh) mem023 mem 0.23h mem02f mem 0.2fh mov bank, #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 mov rpl, #04h ; general register row address 2 sub mem023, mem02f 00001 m r m c r 10 87 43 0 chapter 19 instruction set 210 example 3 to subtract the address 0.6fh contents from the address 0.03h contents and store result in address 0.03h. at this time, data memory address 0.6fh can be specified by selecting data memory address 2fh, if ixe = 1, ixh = 0, ixm = 4, and ixl = 0, i.e., ix = 0.40h. (0.03h) ? (0.03h) + (0.6fh) mem003 mem 0.03h mem02f mem 0.2fh mov bank, #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 mov ixh, #00h ; ix ? 00001000000b (0.40h) mov ixm, #04h ; mov ixl, #00h ; set1 ixe ; ixe flag ? 1 sub mem003, mem02f ; ix 00001000000b (0.40h) ; bank operand or ) 00000101111b (0.2fh) ; specified address 00001101111b (0.6fh) example 4 to subtract the address 0.3fh contents from the address 0.03h contents and store result in address 0.03h. at this time, data memory address 0.3fh can be specified by selecting data memory address 2fh, if ixe = 1, ixh = 0, ixm = 1, and ixl = 0, i.e., ix = 0.10h. (0.03h) ? (0.03h) + (0.3fh) mem003 mem 0.03h mem02f mem 0.2fh mov bank #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 mov ixh, #00h ; ix ? 00000010000b (0.10h) mov ixm, #01h ; mov ixl, #00h ; set1 ixe ; ixe flag ? 1 sub mem003, mem02f ; ix 00000010000b (0.10h) ; bank operand or ) 00000101111b (0.2fh) ; specified address 00000111111b (0.3fh) chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 211 <4> caution the first operand for the sub r, m instruction is a general register address. therefore, if the instruction is described as follows, the general register address is 03h: mem013 mem 0.13h mem02f mem 0.2fh mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 sub mem013, mem02f specify general register in 00hC0fh range (set register pointer row address other than 1). when the cmp flag = 1, the subtraction result is not stored. when the bcd flag = 1, the decimal subtraction result is stored. (2) sub m, #n4 subtract immediate data from data memory <1> op code <2> function when cmp = 0, (m) ? (m) C n4 subtracts immediate data from the data memory contents, and stores the result in data memory. when cmp = 1, (m) C n4 the result is not stored in data memory. carry flag cy and zero flag z are changed, according to the result. sets carry flag cy, if a borrow occurs as a result of the subtraction. resets the carry flag, if no borrow occurs. if the subtraction result is other than zero, zero flag z is reset, regardless of compare flag cmp. if the result is zero with the compare flag reset (cmp = 0), the zero flag z is set. if the result is zero with the compare flag set (cmp = 1), the zero flag z is not changed. subtraction can be executed in binary 4 bits or bcd. the bcd flag for psword specifies which kind of subtraction is to be executed. <3> example 1 to subtract 5 from the address 0.2fh contents, and store the result in address 0.2fh: (0.2fh) ? (0.2fh) C 5 mem02f mem 0.2fh sub mem02f, #05h 10001 m r m c n4 10 87 43 0 chapter 19 instruction set 212 example 2 to subtract 5 from the address 0.6fh contents and store the result in address 0.6fh. at this time, data memory address 0.6fh can be specified by selecting data memory address 2fh, if ixe = 1, ixh = 0, ixm = 4, and ixl = 0, i.e., ix = 0.40h. (0.6fh) ? (0.6fh) C 5 address obtained as a result of oring index register contents, 0.40h, and data memory address 0.2fh mem02f mem 0.2fh mov bank, #00h ; data memory bank 0 mov ixh, #00h ; ix ? 00001000000b (0.40h) mov ixm, #04h ; mov ixl, #00h ; set1 ixe ; ixe flag ? 1 sub mem02f, #05h ; ix 00001000000b (0.40h) ; bank operand or ) 00000101111b (0.2fh) ; specified address 00001101111b (0.6fh) example 3 to subtract 5 from the address 0.2fh contents and store the result in address 0.2fh. at this time, data memory address 0.2fh can be specified by selecting data memory address 2fh, if ixe = 1, ixh = 0, ixm = 0, and ixl = 0, i.e., ix = 0.00h. (0.2fh) ? (0.2fh) C 5 address obtained as a result of oring index register contents, 0.00h, and data memory address 0.2fh mem02f mem 0.2fh mov bank0, #00h ; data memory bank 0 mov ixh, #00h ; ix ? 00000000000b (0.00h) mov ixm, #00h ; mov ixl, #00h ; set1 ixe ; ixe flag ? 1 sub mem02f, #05h ; ix 00000000000b (0.00h) ; bank operand or ) 00000101111b (0.2fh) ; specified address 00000101111b (0.2fh) (3) subc r, m subtract data memory from general register with carry flag <1> op code 00011 m r m c r 10 87 43 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 213 <2> function when cmp = 0, (r) ? (r) C (m) C cy subtracts the data memory contents from the general register contents with carry flag cy. stores the result in general register. by using this subc instruction, 2 or more words can be easily subtracted. when cmp = 1, (r) C (m) C cy the result is not stored in the register. carry flag cy and zero flag z are changed, according to the result. sets carry flag cy, if a borrow occurs as a result of the subtraction. resets the carry flag, if no borrow occurs. if the subtraction result is other than zero, zero flag z is reset, regardless of compare flag cmp. if the result is zero with the compare flag reset (cmp = 0), the zero flag z is set. if the result is zero with the compare flag set (cmp = 1), the zero flag z is not changed. subtraction can be executed in binary 4 bits or bcd. the bcd flag for psword specifies which kind of subtraction is to be executed. <3> example 1 to subtract the 12-bit contents for addresses 0.2dh through 0.2fh from the 12-bit contents for addresses 0.0dh through 0.0fh and store the result in 12 bits for addresses 0.0dh through 0.0fh, when row address 0 (0.00hC0.0fh) in bank 0 is specified as a general register: (0.0fh) ? (0.0fh) C (0.2fh) (0.0eh) ? (0.0eh) C (0.2eh) C cy (0.0dh) ? ( 0.0dh) + (0.2dh) C cy mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mem02d mem 0.2dh mem02e mem 0.2eh mem02f mem 0.2fh sub mem00f, mem02f ; low-order nibble subc mem00e, mem02e subc mem00d, mem02d ; high-order nibble chapter 19 instruction set 214 example 2 to subtract the 12-bit contents for addresses 0.40h through 0.42h from the 12-bit contents for addresses 0.0dh through 0.0fh, and store the result in 12 bits for addresses 0.0dh through 0.0fh: (0.0dh) ? (0.0dh) C (0.40h) (0.0eh) ? (0.0eh) C (0.41h) C cy (0.0fh) ? (0.0fh) + (0.42h) C cy mem000 mem 0.00h mem001 mem 0.01h mem002 mem 0.02h mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mov bank, #00h ; data memory bank 0 mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 mov ixh, #00h ; ix ? 00001000000b (0.40h) mov ixm, #04h ; mov ixl, #00h ; set1 ixe ; ixe flag ? 1 sub memood, mem000 ; (0.0dh) ? (0.0dh) C (0.40h) subc mem00e, mem001 ; (0.0eh) ? (0.0eh) C (0.41h) subc mem00f, mem002 ; (0.0fh) ? (0.0fh) C (0.42h) (4) subc m, #n4 subtract immediate data from data memory with carry flag <1> op code <2> function when cmp = 0, (m) ? (m) C n4 C cy subtracts immediate data from the data memory contents with carry flag cy, and stores the result in data memory. when cmp = 1, (m) C n4 C cy the result is not stored in the register. carry flag cy and zero flag z are changed, according to the result. sets carry flag cy, if a borrow occurs as a result of the subtraction. resets the carry flag, if no borrow occurs. if the subtraction result is other than zero, zero flag z is reset, regardless of compare flag cmp. if the result is zero with the compare flag reset (cmp = 0), the zero flag z is set. if the result is zero with the compare flag set (cmp = 1), the zero flag z is not changed. subtraction can be executed in binary or bcd. the bcd flag for psword specifies which kind of subtraction is to be executed. 10011 m r m c n4 10 87 43 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 215 <3> example 1 to subtract 5 from the 12-bit contents for addresses 0.0dh through 0.0fh and store the result in 12 bits for addresses 0.0dh through 0.0fh: (0.0fh) ? (0.0fh) C 05h (0.0eh) ? (0.0eh) C cy (0.0dh) ? (0.0dh) C cy mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh sub mem00f, #05h subc mem00e, #00h subc mem00d, #00h example 2 to subtract 5 from the 12-bit contents for addresses 0.4dh through 0.4fh and store the result in addresses 0.4dh through 0.4fh: (0.4fh) ? (0.4fh) C 05h (0.4eh) ? (0.4eh) C cy (0.4dh) ? (0.4dh) C cy mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mov bank, #00h ; data memory bank 0 mov ixh, #00h ; ix ? 00001000000b (0.40h) mov ixm, #04h ; mov ixl, #00h ; set1 ixe ; ixe flag ? 1 sub mem00f, #5 ; (0.4fh) ? (0.4fh) C 5 subc mem00e, #0 ; (0.4eh) ? (0.4eh) C cy subc mem00d, #0 ; (0.4dh) ? (0.4dh) C cy chapter 19 instruction set 216 19.5.3 logical operation instructions (1) or r, m or between general register and data memory <1> op code <2> function (r) ? (r) v (m) ors the general register contents with data memory. stores the result in general register. <3> example 1 to or the address 0.03h contents (1010b) and the address 0.2fh contents (0111b) and store the result (1111b) in address 0.03h: (0.03h) ? (0.03h) v (0.2fh) mem003 mem 0.03h mem02f mem 0.2fh mov mem003, #1010b mov mem02f, #0111b or mem003, mem02f (2) or m, #n4 or between data memory and immediate data <1> op code 10110 m r m c n4 10 87 43 0 1 010 or 0111 1111 address 03h address 2fh address 03h 00110 m r m c r 10 87 43 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 217 <2> function (m) ? (m) v n4 ors the data memory contents and immediate data. stores the result in data memory. <3> example 1 to set bit 3 (msb) for address 0.03h: (0.03h) ? (0.03h) v 1000b mem003 mem 0.03h or mem003, #1000b example 2 to set all the bits for address 0.03h: mem003 mem 0.03h or mem003, #1111b or, mem003 mem 0.03h mov mem003, #0fh (3) and r, m and between general register and data memory <1> op code <2> function (r) ? (r) (m) ands the general register contents with data memory and stores the result in general register. v 00100 m r m c r 10 87 43 0 1 : don't care address 0.03h chapter 19 instruction set 218 <3> example to and the address 0.03h (1010b) contents and the address 0.2fh (0110b) contents. to store the result (0010b) in address 0.03h: (0.03h) ? (0.03h) (0.2fh) mem003 mem 0.03h mem02f mem 0.2fh mov mem003, #1010b mov mem02f, #0110b and mem003, mem02f (4) and m, #n4 and between data memory and immediate data <1> op code <2> function (m) ? (m) n4 ands the data memory contents and immediate data. stores the result in data memory. <3> example 1 to reset bit 3 (msb) for address 0.03h: (0.03h) ? (0.03h) 0111b mem003 mem 0.03h and mem003, #0111b v v v 1 010 and 0110 0010 address 03h address 2fh address 03h 11110 m r m c n 10 87 43 0 0 : don't care address 0.03h chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 219 example 2 to reset all the bits for address 0.03h: mem003 mem 0.03h and mem003, #0000b or, mem003 mem 0.03h mov mem003, #00h (5) xor r, m exclusive or between general register and data memory <1> op code <2> function (r) ? (r) v (m) exclusive-ors the general register contents with data memory. stores the result in general register. <3> example 1 to compare the address 0.03h contents and the address 0.0fh contents. if different bits are found, set and store them in address 0.03h. if all the bits in address 0.03h are reset (i.e., the address 0.03h contents are the same as those for address 0.0fh), jumps to lbl1; otherwise, jumps to lbl2. this example is for processing to compare the status of an alternate switch (address 0.03h contents) with the internal status (address 0.0fh contents) and to branch to another processing, if the switch status changes. mem003 mem 0.03h mem00f mem 0.0fh xor mem003, mem00f skne mem003, #00h br lbl1 br lbl2 00101 m r m c r 10 87 43 0 1 010 xor 0110 1100 address 03h address 0fh address 03h bits changed chapter 19 instruction set 220 example 2 to clear the address 0.03h contents: mem003 mem 0.03h xor mem003, mem003 (6) xor m, #n4 exclusive or between data memory and immediate data <1> op code <2> function (m) ? (m) v n4 exclusive-ors the data memory contents and immediate data. stores the result in data memory. <3> example to invert bits 1 and 3 in address 0.03h and store the result in address 03h: mem003 mem 0.03h xor mem003, #1010b 0 101 xor 0101 0000 address 03h address 03h address 03h 10101 m r m c n4 10 87 43 0 1 100 xor 1010 0110 address 03h address 03h inverted bits chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 221 19.5.4 judgment instructions (1) skt m, #n skip next instruction if data memory bits are true <1> op code <2> function cmp ? 0, if (m) n = n, then skip skips the next one instruction, if the result of anding the data memory contents and immediate data is equal to n. (executes as nop instruction) <3> example 1 to jump to aaa, if bit 0 in address 03h is 1; if it is 0, jumps to bbb: skt 03h, #0001b br bbb br aaa example 2 to skip the next instruction, if both bits 0 and 1 in address 03h are 1. skt 03h, #0011b example 3 the results of executing the following two instructions are the same: skt 13h, #1111b ske 13h, #0fh (2) skf m, #n skip next instruction if data memory bits are false <1> op code v 11110 m r m c n 10 87 43 0 11111 m r m c n 10 87 43 0 11 skip condition 03h : don't care b 3 b 2 b 1 b 0 chapter 19 instruction set 222 <2> function cmp ? 0, if (m) n = 0, then skip skips the next one instruction, if the result of anding the data memory contents and immediate data is 0 (executes as nop instruction). <3> example 1 to store immediate data 00h to address 0fh in the data memory, if bit 2 in address 13h is 0; if it is 1, jumps to abc: mem013 mem 0.13h mem00f mem 0.0fh skf mem013, #0100b br abc mov mem00f, #00h example 2 to skip the next instruction, if both bits 3 and 0 in address 29h are 0. skf 29h, #1001b example 3 the results of executing the following two instructions are the same: skf 34h, #1111b ske 34h, #00h v 0 0 skip condition 29h : don't care b 3 b 2 b 1 b 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 223 19.5.5 comparison instructions (1) ske m, #n4 skip if data memory equal to immediate data <1> op code <2> function (m) Cn4, skip if zero skips the next one instruction, if the data memory contents are equal to the immediate data value (executes as nop instruction). <3> example to transfer 0fh to address 24h, if the address 24h contents are 0; if not, jumps to ope1: mem024 mem 0.24h ske mem024, #00h br ope1 mov mem024, #0fh ope1 : (2) skne m, #n4 skip if data memory not equal to immediate data <1> op code <2> function (m) Cn4, skip if not zero skips the next one instruction, if the data memory contents are not equal to the immediate data value (executes as nop instruction). 01001 m r m c n4 10 87 43 0 01011 m r m c n4 10 87 43 0 chapter 19 instruction set 224 <3> example to jump to xyz, if the asddress 1fh contents are 1 and the address 1eh contents are 3; otherwise, jump to abc. to compare 8-bit data, this instruction is used in the following combination: mem01e mem 0.1eh mem01f mem 0.1fh skne mem01f, #01h ske mem01e, #03h br abc br xyz the above program can be rewritten as follows, using compare and zero flags: mem01e mem 0.1eh mem01f mem 0.1fh set2 cmp, z ; cmp flag ? 1, z flag ? 1 sub mem01f, #01h subc mem01e, #03h skt1 z br abc br xyz (3) skge m, #n4 skip if data memory greater than or equal to immediate data <1> op code <2> function (m) Cn4, skip if not borrow skips the next one instruction, if the data memory contents are greater than or equal to the immediate data value (executes as nop instruction). 0011 3 1eh 0001 1 1fh 11001 m r m c n4 10 87 43 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 225 <3> example to execute ret, if 8-bit data stored in addresses 1fh (high-order) and 2fh (low-order) is greater than immediate data 17h; if not, execute retsk: mem01f mem 0.1fh mem02f mem 0.2fh skge mem01f, #1 retsk skne mem01f, #1 sklt mem02f, #8 ; 7 + 1 ret retsk (4) sklt m, #n4 skip if data memory less than immediate data <1> op code <2> function (m) Cn4, skip if borrow skips the next one instruction, if the data memory contents are less than the immediate data value (executes as nop instruction). <3> example to store 01h in address 0fh, if the address 10h contents are greater than immediate data 6; if not, store 02h in address 0fh: mem00f mem 0.0fh mem010 mem 0.10h mov mem00f, #02h sklt mem010, #06h mov mem00f, #01h 11011 m r m c n4 10 87 43 0 chapter 19 instruction set 226 19.5.6 rotation instructions (1) rorc r rotate right general register with carry flag <1> op code <2> function rotates the contents of general register indicated by r to right by 1 bit including carry flag. <3> example 1 when row address 0 of bank 0 (0.00h C 0.0fh) is specified as general register (rph = 0, rpl = 0), rotate the value of address 0.00h (1000b) to right by 1 bit to make it 0100b. (0.00h) ? (0.00h) ? 2 mem000 mem 0.00h mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 clr1 cy ; cy flag ? 0 rorc mem000 example 2 when row address 0 of bank 0 (0.00h C 0.0fh) is specified as general register (rph = 0, rpl = 0), rotate the data buffer dbf contents 0fa52h to right by 1 bit to make dbf contents 7d29h. mem00c mem 0.0ch mem00d mem 0.0dh mem00e mem 0.0eh mem00f mem 0.0fh mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 clr1 cy ; cy flag ? 0 rorc mem00c rorc mem00d rorc mem00e rorc mem00f 00111 000 0111 r 30 cy (r) b3 (r) b2 (r) b1 (r) b0 cy 0 0ch 1111 0dh 1010 0eh 0101 0fh 0010 cy 0 0111 1101 0010 1001 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 227 19.5.7 transfer instructions (1) ld r, m load data memory to general register <1> op code <2> function (r) ? (m) stores the data memory contents to general register. <3> example 1 to store the address 0.2fh contents to address 0.03h: (0.03h) ? (0.2fh) mem003 mem 0.03h mem02f mem 0.2fh mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 ld mem003, mem02f 01000 m r m c r 10 87 43 0 system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address general register column address bank 0 chapter 19 instruction set 228 example 2 to store the address 0.6fh contents to address 0.03h. at this time, data memory address 0.6fh can be specified by selecting data memory address 2fh, if ixe = 1, ixh = 0, ixm = 4, and ixl = 0, i.e., ix = 0.40h. ixh ? 00h ixm ? 04h ixl ? 00h ixe flag ? 1 (0.03h) ? (0.6fh) address obtained as result of oring index register contents, 040h, and data memory contents, 0.2fh mem003 mem 0.03h mem02f mem 0.2fh mov ixh, #00h ; ix ? 00001000000b (0.40h) mov ixm, #04h mov ixl, #00h set1 ixe ; ixe flag ? 1 ld mem003, mem02f (2) st m, r store general register to data memory <1> op code <2> function (m) ? (r) stores the general register contents to data memory. 11000 m r m c r 10 87 43 0 system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address general register column address bank 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 229 . . . . . . . . . . . <3> example 1 to store the address 0.03h contents to address 0.2fh: (0.2fh) ? (0.03h) mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 st 2fh, 03h ; transfers general register contents to data memory example 2 to store the address 0.00h contents to addresses 0.18h through 0.1fh. the data memory addresses (18h C 1fh) are specified by the index register. (0.18h) ? (0.00h) (0.19h) ? (0.00h) (0.1fh) ? (0.00h) mov ixh, #00h ; ix ? 00000000000b (0.00h) mov ixm, #00h mov ixl, #00h ; specifies data memory address 0.00h mem018 mem 0.18h mem000 mem 0.00h loop1: set1 ixe ; ixe flag ? 1 st mem018, mem000 ; (0.1 5 h) ? (0.00h) clr1 ixe ; ixe flag ? 0 inc ix ; ix ? ix + 1 skge ixl, #08h br loop1 system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address general register column address bank 0 chapter 19 instruction set 230 (3) mov @r, m move data memory to destination indirect <1> op code <2> function when mpe = 1 ((mp), (r)) ? (m) when mpe = 0 (bank, m r , (r)) ? (m) stores the data memory contents to the data memory addressed by the general register contents. when mpe = 0, transfer is performed in the same row address in the same bank. <3> example 1 to store the address 0.20h contents to address 0.2fh with the mpe flag cleared to 0. the transfer destination data memory address is at the same row address as the transfer source, and the column address is specified by the general register contents at address 0.00h. (0.2fh) ? (0.20h) mem000 mem 0.00h mem020 mem 0.20h clr1 mpe ; mpe flag ? 0 mov mem000, #0fh ; sets column address in general register mov @mem000, mem020 ; store 01010 m r m c r 10 87 43 0 system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address general register column address bank 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 231 example 2 to store the address 0.20h contents to address 0.3fh, with the mpe flag set to 1. the row address for the transfer destination data memory address is specified by the memory pointer mp contents. the column address is specified by the general register contents at address 0.00h. (0.3fh) ? (0.20h) mem000 mem 0.00h mem020 mem 0.20h mov rph, #00h ; general register bank 0 mov rpl, #00h ; general register row address 0 mov mem000, #0fh ; sets column address in general register mov mph, #00h ; sets row address in memory pointer mov mpl, #03h ; set1 mpe ; mpe flag ? 1 mov @mem000, mem020 ; store (4) mov m, @r move data memory to destination indirect <1> op code 11010 m r m c r 10 87 43 0 system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address general register column address bank 0 f system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address general register column address bank 0 f chapter 19 instruction set 232 <2> function when mpe = 1 (m) ? (mp, (r)) when mpe = 0 (m) ? (bank, m r , (r)) stores the data memory contents addressed by the general register contents to data memory. when mpe = 0, transfer is performed in the same row address in the same bank. <3> example 1 to store the address 0.2fh contents to address 0.20h, with the mpe flag cleared to 0. the transfer destination data memory address is at the same row address as the transfer source. the column address is specified by the general register contents at address 0.00h. (0.20h) ? (0.2fh) mem000 mem 0.00h mem020 mem 0.20h clr1 mpe ; mpe flag ? 0 mov mem000, #0fh ; sets column address in general register mov mem020, @mem000 ; store example 2 to store the address 0.3fh contents to address 0.20h, with the mpe flag set to 1. the row address for the transfer source data memory address is specified by the memory pointer mp contents. the column address is specified by the general register contents at address 0.00h. (0.20h) ? (0.3fh) mem000 mem 0.00h mem020 mem 0.20h mov mem000, #0fh ; sets column address in general register mov mph, #00h ; sets row address in memory pointer mov mpl, #03h ; set1 mpe ; mpe flag ? 1 mov mem020, @mem000 ; store system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address general register column address bank 0 f chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 233 (5) mov m, #n4 move immediate data to data memory <1> op code <2> function (m) ? n4 stores immediate data to data memory. <3> example 1 to store immediate data 0ah to data memory address 0.50h: (0.5h) ? 0ah mem050 mem 0.50h mov mem050, #0ah example 2 to store immediate data 07h to address 0.32h, when data memory address 0.00h is specified with ixh = 0, ixm = 3, ixl = 2, and ixe flag = 1: (0.32h) ? 07h mem000 mem 0.00h mov ixh, #00h ; ix ? 00000110010b (0.32h) mov ixm, #03h mov ixl, #02h set1 ixe ; ixe flag ? 1 mov mem000, #07h 11101 m r m c n4 10 87 43 0 system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address general register column address bank 0 f chapter 19 instruction set 234 (6) movt dbf, @ar move program memory data specified by ar to dbf <1> op code <2> function sp ? sp C 1, asr ? pc, pc ? ar, dbf ? (pc), pc ? asr, sp ? sp + 1 stores the program memory contents, addressed by address register ar, to data buffer dbf. since this instruction temporarily uses one stack level, pay attention to nesting for subroutines and interrupts. <3> example to transfer 16 bits of table data, specified by the values for address registers ar3, ar2, ar1, and ar0 in the system register, to data buffers dbf3, dbf2, dbf1, and dbf0: ; * ; ** table data ; * org 0010h dw 0000000000000000b ; (0000h) dw 1010101111001101b ; ( 0abcdh) ; * ; ** table reference program ; * mov ar3, #00h ; ar3 ? 00h sets 0011h in address register mov ar2, #00h ; ar2 ? 00h mov ar1, #01h ; ar1 ? 01h mov ar0, #01h ; ar0 ? 01h movt dbf, @ar ; transfers address 0011h data to dbf in this case, the data are stored in dbf, as follows: dbf3 = 0ah dbf2 = 0bh dbf1 = 0ch dbf0 = 0dh . . . . . . . . . . 00111 000 0001 0000 10 87 43 0 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 235 (7) push ar push address register <1> op code <2> function sp ? sp C 1, asr ? ar decrements stack pointer sp and stores the address register ar value to address stack register specified by stack pointer. <3> example 1 to set 003fh in address register and store it in stack: mov ar3, #00h mov ar2, #00h mov ar1, #03h mov ar0, #0fh push ar 00111 000 1101 0000 system register 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address column address bank 0 003f c sta k 003f chapter 19 instruction set 236 example 2 to set the return address (next address of the data table) for a subroutine in the address register. returns execution, if a data table exists after a subroutine: sub1: pop mov mov mov mov push ret if pop instruction is executed at this time, the contents of address register is 0011h (the next address of call instruction). ............ call org ;* ;** data table ;* dw dw dw dw 1a1fh 002fh 010ah 0555h .................. dw org 0fffh 30h .................. sub1 10h ............ ar ar3, #00h ar2, #00h ar1, #03h ar0, #00h ar chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 237 (8) pop ar pop address register <1> op code <2> function ar ? asr, sp ? sp + 1 pops the contents of address stack register indicated by stack pointer to address register ar and then increments stack pointer sp. <3> example if the psw contents are changed, while an interrupt processing routine is being executed, the psw contents are transferred to the address register through wr at the beginning of the interrupt processing and saved to address stack register by the push instruction. before the execution returns from the interrupt routine, the address register contents are restored through wr to psw by the pop instruction. 00111 000 1100 0000 peek poke push .................... ei interrupt processing routine wr, psw ar0, wr ar ........................................... pop peek poke ret (or reti) ar wr, ar0 psw, wr ................... .................................................... generates interrupt source chapter 19 instruction set 238 (9) peek wr, rf peek register file to window register <1> op code <2> function wr ? (rf) stores the register file contents to window register wr. <3> example 1 to store the stack pointer sp contents at address 01h in the register file to the window register: peek wr, sp 00111 rf r 0011 10 87 43 0 rf c 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address column address bank 0 wr system register 0 1 2 3 0f 1 23456789abcde row address column address register file sp chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 239 (10) poke rf, wr poke window register to register file <1> op code <2> function (rf) ? wr stores the window register wr contents to register file. <3> example to store immediate data 0fh to p0dbio for the register file through the window register: mov wr, #0fh poke p0dbio, wr ; sets all of p0d 0 , p0d 1 , p0d 2 , and p0d 3 in output mode 00111 rf r 0010 10 87 43 0 rf c 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address column address bank 0 wr system register 0 1 2 3 0f 1 23456789abcde row address column address register file p0dbio chapter 19 instruction set 240 <4> caution it seems that the same addresses 40h through 7fh of the data memory exist at addresses 40h through 7fh of the register file as for as the program is concerned. the peek and poke instructions can access addresses 40h through 7fh in each data memory bank, in addition to the register file. for example, these instructions can be used as follows: mem05f mem 0.5fh peek wr, psw ; stores psw (7fh) contents in system register to wr poke mem05f, wr ; stores wr contents to address 5fh in data memory (11) get dbf, p get peripheral data to data buffer <1> op code <2> function dbf ? (p) stores the peripheral register contents to data buffer dbf. dbf is a 16-bit area of addresses 0h through 0fh of bank0 of the data memory regardless of the value of the bank register. <3> example to store the 8-bit contents for shift register siosfr in the serial interface to data buffers dbf0 and dbf1: get dbf, siosfr 00111 p h 1011 10 87 43 0 p l 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address column address bank 0 wr psw peek wr, psw poke 5fh, wr register file data memory system register chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 241 <4> caution the data buffer is configured in 16 bits. however, the number of bits accessed differs depending on the peripheral hardware. for example, if the get instruction is executed to a peripheral hardware register with a valid bit length of 8 bits, the contents of the peripheral hardware register are stored to the low-order 8 bits (dbf1, dbf0) of the data buffer dbf. (12) put p, dbf put data buffer peripheral <1> op code <2> function (p) ? dbf stores the data buffer dbf contents to peripheral hardware register. dbf is a 16-bit area of addresses 0h through 0fh of bank0 of the data memory regardless of the value of the bank register. data buffer actual bits b 7 b 0 get b 7 b 0 dbf0 dbf1 dbf2 retained dbf3 retained peripheral hardware register 00111 1010 p l 10 87 43 0 p h 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address column address bank 0 dbf 12 system register siosfr 12h peripheral hardware register chapter 19 instruction set 242 <3> example to set 0ah and 05h to data buffers dbf1 and dbf0, respectively, and transfer them to a peripheral register, shift register (siosfr) for serial interface: mov bank, #00h ; data memory bank 0 mov dbf0, #05h mov dbf1, #0ah put siosfr, dbf <4> caution the data buffer is configured in 16 bits. however, the number of bits accessed differs depending on the peripheral hardware. for example, if the get instruction is executed to a peripheral hardware register with a valid bit length of 8 bits, the contents of the peripheral hardware register are stored to the low-order 8 bits (dbf1, dbf0) of the data buffer dbf. data buffer actual bits b 7 b 0 put b 7 b 0 dbf0 dbf1 dbf2 don't care dbf3 don't care peripheral hardware register b 6 b 5 b 4 b 3 b 2 b 1 0 1 2 3 4 5 6 7 0f 1 23456789abcde row address column address bank 0 dbf a5 system register siosfr 0a5h peripheral hardware register chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 243 19.5.8 branch instructions (1) br addr branch to the address <1> op code <2> function pc ? addr branches to an address specified by addr. <3> example fly lab 0fh ; defines fly = 0fh : : br fly ; jumps to address 0fh : : br loop1 ; jumps to loop1 : : br $ + 2 ; jumps to an address 2 addresses lower than current address : : bf $ C 3 ; jumps to an address 3 addresses higher than current address : : loop1: (2) br @ar branch to the address specified by address register <1> op code <2> function pc ? ar branches to the program address, specified by address register ar. 01100 addr 0 10 00111 000 0100 0000 chapter 19 instruction set 244 <3> example 1 to set 003fh in address register ar (ar0 C ar3) and jump to address 003fh by using the br @ar instruction: mov ar3, #00h ; ar3 ? 00h mov ar2, #00h ; ar2 ? 00h mov ar1, #03h ; ar1 ? 03h mov ar0, #0fh ; ar0 ? 0fh br @ar ; jumps to address 003fh example 2 to change the branch destination according to the data memory address 0.10h contents, as follows: 0.10h contents branch destination label 00h ? aaa 01h ? bbb 02h ? ccc 03h ? ddd 04h ? eee 05h ? fff 06h ? ggg 07h ? hhh 08h C 0fh ? zzz ; * ; ** jump table ; * org 10h br aaa br bbb br ccc br ddd br eee br fff br ggg br hhh br zzz : : : mem010 mem 0.10h mov ar3, #00h ; ar3 ? 00h sets ar to 001 5 h mov ar2, #00h ; ar2 ? 00h mov ar1, #01h ; ar1 ? 01h mov rph, #00h ; general register bank 0 mov rpl, #02h ; general register row address 1 st ar0, mem010 ; ar0 ? 0.10h sklt ar0, #08h mov ar0, #08h ; sets 08h in ar0, if ar0 contents are greater br @ar ; than 08h chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 245 <4> caution the number of bits, for address register ar3, ar2, ar1, and ar0, differs, depending on the microcontroller model to be used. ? m pd17134a/17135a : 10 bits ? m pd17136a/17137a/17p136a/17p137a : 11 bits chapter 19 instruction set 246 19.5.9 subroutine instructions (1) call addr call subroutine <1> op code <2> function sp ? sp C 1, asr ? pc, pc ? addr increments and stores the program counter pc value to stack, and branches to a subroutine specified by addr. <3> example 1 example 2 11100 addr 0 10 .................... sub1: ret ................... main call sub1 ............ ........... sub1: ............... main call sub1 ............ call sub2 ........... ret ........... sub2: call sub3 ........... ret .............................. sub3: ret chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 247 (2) call @ar call subroutine specified by address register <1> op code <2> function sp ? sp C 1, asr ? pc, pc ? ar saves the program counter pc value to the stack, and branches the execution to a subroutine that starts from the address specified by address register ar. <3> example 1 to set 0020h in address register ar (ar0Car3) and call the subroutine at address 0020h with the call @ar instruction: mov ar3, #00h ; ar3 ? 00h mov ar2, #00h ; ar2 ? 00h mov ar1, #02h ; ar1 ? 02h mov ar0, #00h ; ar0 ? 00h call @ar ; calls subroutine at address 0020h example 2 to call the following subroutine by the data memory address 0.10h contents: contents of 0.10h subroutine 00h ? sub1 01h ? sub2 02h ? sub3 03h ? sub4 04h ? sub5 05h ? sub6 06h ? sub7 07h ? sub8 08hC0fh ? sub9 00111 000 0101 0000 chapter 19 instruction set 248 <4> caution the number of bits, in address registers ar3, ar2, ar1, and ar0, differs, depending on the microcontroller model to be used. ? m pd17134a/17135a : 10 bits ? m pd17136a/17137a/17p136a/17p137a : 11 bits sub1: .................................... ret sub2: .................................... ret sub3: .................................... ret sub7: .................................... ret sub8: .................................... ret sub9: .................................... ret sub6: .................................... ret .................................... sub4: .................................... ret sub5: .................................... ret ........... ........... ;* ;**jump table for subroutine ;* ........... mov mov mov mov mov st sklt mov call ar3, ar2, ar1, rph, rpl, ar0, ar0, ar0, @ar #00h #00h #01h #00h #02h 10h #08h #08h ; ar3 00h address register 001 h ; ar2 00h ; ar1 01h ; general register bank 0 ; general register row address 1 ; ar0 0.10h ; if ar0 is larger than 08h, ; set ar0 to 08h to jump table returns here when executing ret instruction in each subroutine ................ org br br br br br br br br br 10h sub1 sub2 sub3 sub4 sub5 sub6 sub7 sub8 sub9 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 249 (3) ret return to the main program from subroutine <1> op code <2> function pc ? asr, sp ? sp + 1, instruction to return to the main program from a subroutine. restores the return address, saved to the stack by the call instruction, to the program counter. <3> example (4) retsk return to the main program then skip next instruction <1> op code <2> function pc ? asr, sp ? sp + 1 and skip instruction to return to the main program from a subroutine. skips the instruction next to the call instruction (i.e., treats that instructions as an nop instruction). therefore, restores the return address, saved to the stack by the call instruction, to program counter pc and then increments the program counter. 00111 000 1110 0000 10 87 43 0 call sub1 .................... .................... sub1: ret .............................. 00111 001 1110 0000 chapter 19 instruction set 250 <3> example to execute the ret instruction, if the lsb (least significant bit) content for address 25h in the data memory (ram) is 0. the execution is returned to the instruction next to the call instruction. if the lsb is 1, execute the retsk instruction. the execution is returned to the instruction following the one next to the call instruction (in this example, add 03h, 16h). (5) reti return to the main program from the interrupt service routine <1> op code <2> function pc ? asr, intr ? intsk, sp ? sp + 1 instruction to return to the main program, from an interrupt service routine. restores the return address, saved to the stack by a vector interrupt, to the program counter. part of the system register (bank, psword) is also returned to the status before the occurrence of the vector interrupt. call .................... .................... sub1: skf 25h, #0001b .............................. br add sub1 loop 03h, 16h retsk ret ; lsb of 25h is "1" ; lsb of 25h is "0" 00111 100 1110 0000 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 251 19.5.10 interrupt instructions (1) ei enable interrupt <1> op code <2> function intef ? 1 enables a vectored interrupt. the interrupt is enabled after the instruction next to the ei instruction has been executed. <3> example 1 as shown in the following example, the interrupt is accepted after the instruction next to that, that has accepted the interrupt, has been completely executed (excluding an instruction that manipulates program counter). the flow then shifts to the vector address note1 . 00111 000 1111 0000 ei ............ mov ....................... ................ add add 0ah, 0bh, 0ch, #00h #01h #01h generating interrupt request generating interrupt request di ei ............ ........... mov sub 0ah, 0bh, #01h #01h ei ret .................... note 2 interrupt service routine (vector address) chapter 19 instruction set 252 notes 1. the vector address differs, depending on the interrupt to be accepted. refer to table 14-1 . 2. the interrupt accepted in this example (an interrupt request is generated after the ei instruction has been executed and the execution flow shifts to an interrupt service routine) is the interrupt, whose interrupt enable flag (ip ) is set. the program flow is not changed, without the interrupt enable flag set, even if an interrupt request is generated, after the ei instruction has been executed (therefore, the interrupt is not accepted). however, interrupt request flag (irq ) is set, and the interrupt is accepted, as soon as the interrupt enable flag is set. example 2 an example of an interrupt, which occurs in response to an interrupt request being accepted counter pc is being executed: (2) di disable interrupt <1> op code <2> function intef ? 0 instruction to disable a vectored interrupt. <3> example refer to example 1 in (1) ei. ei ............ ................. ................ abc generating interrupt request ............. ei ret .................... interrupt service routine (vector address) mov add 0ah, #00h 0bh, #01h br abc: 00111 001 1111 0000 chapter 19 instruction set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 253 19.5.11 other instructions (1) stop s stop cpu and release by condition s <1> op code <2> function stops the system clock and places the device in the stop mode. in the stop mode, the power consumption for the device is minimized. the condition, under which the stop mode is to be released, is specified by operand (s). for the stop releasing condition (s), refer to 16.3 stop mode . (2) halt h halt cpu and release by condition h <1> op code <2> function places the device in the halt mode. in the halt mode, the power consumption for the device is reduced. the condition, under which the halt mode is to be released, is specified by operand (h). for halt releasing condition (h), refer to 16.2 halt mode . (3) nop no operation <1> op code <2> function performs nothing and consumes one machine cycle. 00111 010 1111 s 30 00111 011 1111 h 30 00111 100 1111 0000 [memo] 254 chapter 20 assembler reserved words 20.1 mask option directive the m pd173134a, 17135a, 17136a, and 17137a have the following mask options. ? internal pull-up resistor of reset pin ? internal pull-up resistor of p0d 3 through p0d 0 pins ? internal pull-up resistor of p1a 3 through p1a 0 pins ? internal pull-up resistor of p1b 0 pin when developing a program, all the above mask options must be specified in the source program by using mask option directives. 20.1.1 specifying mask option the mask options are described in the assembler source program by using the following directives. ? option and endop directives ? mask option definition directive (1) option and endop directives these directives specify the range in which the mask option is to be described (mask option definition block). specify the mask option by describing the mask option directive in an area between the option and endop directives. description format symbol field mnemonic field operand field comment field [label: ] option [;comment] endop . . . . . . 255 chapter 20 assembler reserved words 256 (2) mask option definition directive table 20-1. mask option definition directive option definition directive and format operand definition internal pull-up resistor optres chapter 20 assembler reserved words 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 257 20.2 reserved symbols the reserved symbols defined in the m pd17134a, 17135a, 17136a, and 17137a device file (as17134) are listed below. system register (sysreg) mem mem mem mem mem mem mem mem flg mem mem mem mem mem mem flg flg flg flg flg 0.74h 0.75h 0.76h 0.77h 0.78h 0.79h 0.7ah 0.7ah 0.7ah.3 0.7bh 0.7bh 0.7ch 0.7dh 0.7eh 0.7fh 0.7eh.0 0.7fh.3 0.7fh.2 0.7fh.1 0.7fh.0 r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 12 of the address register bits 11 to 8 of the address register bits 7 to 4 of the address register bits 3 to 0 of the address register window register bank register index register high data memory row address pointer high memory pointer enable flag index register middle data memory row address pointer low index register low general register pointer high general register pointer low program status word bcd flag compare flag carry flag zero flag index enable flag read/ write description value symbolic name ar3 ar2 ar1 ar0 wr bank ixh mph mpe ixm mpl ixl rph rpl psw bcd cmp cy z ixe attribute chapter 20 assembler reserved words 258 data buffer (dbf) port register dbf3 dbf2 dbf1 dbf0 mem mem mem mem 0.0ch 0.0dh 0.0eh 0.0fh r/w r/w r/w r/w dbf bits 15 to 12 dbf bits 11 to 8 dbf bits 7 to 4 dbf bits 3 to 0 read/ write description value symbolic name p0a3 p0a2 p0a1 p0a0 p0b3 p0b2 p0b1 p0b0 p0c3 p0c2 p0c1 p0c0 p0d3 p0d2 p0d1 p0d0 p1a3 p1a2 p1a1 p1a0 p1b0 flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg 0.70h.3 0.70h.2 0.70h.1 0.70h.0 0.71h.3 0.71h.2 0.71h.1 0.71h.0 0.72h.3 0.72h.2 0.72h.1 0.72h.0 0.73h.3 0.73h.2 0.73h.1 0.73h.0 1.70h.3 1.70h.2 1.70h.1 1.70h.0 1.71h.0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r port 0a bit 3 port 0a bit 2 port 0a bit 1 port 0a bit 0 port 0b bit 3 port 0b bit 2 port 0b bit 1 port 0b bit 0 port 0c bit 3 port 0c bit 2 port 0c bit 1 port 0c bit 0 port 0d bit 3 port 0d bit 2 port 0d bit 1 port 0d bit 0 port 1a bit 3 port 1a bit 2 port 1a bit 1 port 1a bit 0 port 1b bit 0 read/ write symbolic name value description attribute attribute C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC chapter 20 assembler reserved words 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 259 register file (control register) symbolic name attribute value description sp siots siohiz siock1 siock0 wdtres wdten tm0osel sioen p0bgpu p0agpu int pdresen tm0en tm0res tm0ck1 tm0ck0 tm1en tm1res tm1ck1 tm1ck0 btmisel btmres btmck1 btmck0 p0c3idi p0c2idi p0c1idi p0c0idi p0cbio3 p0cbio2 p0cbio1 p0cbio0 zcross iegmd1 iegmd0 adcstrt adcsoft adccmp adcend mem flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg 0.81h 0.82h.3 0.82h.2 0.82h.1 0.82h.0 0.83h.3 0.83h.0 0.8bh.3 0.8bh.0 0.8ch.1 0.8ch.0 0.8fh.0 0.90h.0 0.91h.3 0.91h.2 0.91h.1 0.91h.0 0.92h.3 0.92h.2 0.92h.1 0.92h.0 0.93h.3 0.93h.2 0.93h.1 0.93h.0 0.9bh.3 0.9bh.2 0.9bh.1 0.9bh.0 0.9ch.3 0.9ch.2 0.9ch.1 0.9ch.0 0.9dh.0 0.9fh.1 0.9fh.0 0.0a0h.0 0.0a1h.3 0.0a1h.1 0.0a1h.0 read/ write stack pointer sio start flag so pin state sio source clock selection flag bit 1 sio source clock selection flag bit 0 watchdog timer reset flag watchdog timer enable flag flag for switching timer 0 output and port sio enable flag p0b group pull-up selection flag (pull-up = 1) p0a group pull-up selection flag (pull-up = 1) int pin status flag power-down reset enable flag timer 0 enable flag timer 0 reset flag timer 0 source clock selection flag bit 1 timer 0 source clock selection flag bit 0 timer 1 enable flag timer 1 reset flag timer 1 source clock selection flag bit 1 timer 1 source clock selection flag bit 0 btm interrupt request clock selection flag btm reset flag btm source clock selection flag bit 1 btm source clock selection flag bit 0 p0c 3 input port disable flag (adc 3 /p0c 3 selection) p0c 2 input port disable flag (adc 2 /p0c 2 selection) p0c 1 input port disable flag (adc 1 /p0c 1 selection) p0c 0 input port disable flag (adc 0 /p0c 0 selection) p0c 3 input/output selection flag (1 = output port) p0c 2 input/output selection flag (1 = output port) p0c 1 input/output selection flag (1 = output port) p0c 0 input/output selection flag (1 = output port) zerocross detector enable flag int pin edge detection selection flag bit 1 int pin edge detection selection flag bit 0 a/d converter start flag (always 0 when read) a/d converter software control flag (1 = single mode) a/d converter comparison result flag (valid only in single mode) a/d converter conversion end flag r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC chapter 20 assembler reserved words 260 peripheral register flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg flg 0.0a2h.3 0.0a2h.2 0.0a2h.1 0.0a2h.0 0.0abh.3 0.0abh.2 0.0abh.1 0.0abh.0 0.0ach.2 0.0ach.1 0.0ach.0 0.0aeh.0 0.0afh.3 0.0afh.2 0.0afh.1 0.0afh.0 0.0bbh.0 0.0bch.0 0.0bdh.0 0.0beh.0 0.0bfh.0 read/ write symbolic name attribute value description r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dummy flag dummy flag a/d converter channel selection flag bit 1 a/d converter channel selection flag bit 0 p0d 3 input/output selection flag (1 = output port) p0d 2 input/output selection flag (1 = output port) p0d 1 input/output selection flag (1 = output port) p0d 0 input/output selection flag (1 = output port) p1a group input/output selection flag (1 = all p1as are output ports.) p0b group input/output selection flag (1 = all p0bs are output ports.) p0a group input/output selection flag (1 = all p0as are output ports.) sio interrupt enable flag btm interrupt enable flag tm1 interrupt enable flag tm0 interrupt enable flag int pin interrupt enable flag sio interrupt request flag btm interrupt request flag tm1 interrupt request flag tm0 interrupt request flag int pin interrupt request flag adcch3 adcch2 adcch1 adcch0 p0dbio3 p0dbio2 p0dbio1 p0dbio0 p1agio p0bgio p0agio ipsio ipbtm iptm1 iptm0 ip irqsio irqbtm irqtm1 irqtm0 irq dat dat dat dat dat dat 01h 02h 03h 04h 45h 40h read/ write symbolic name attribute value description r/w w w r/w r r/w peripheral address of the shift register peripheral address of the timer 0 modulo register peripheral address of the timer 1 modulo register peripheral address of a/d converter data register peripheral address of timer 0 timer 1 count register peripheral address of the address register for get, put, push, call, br, movt, and inc instructions siosfr tm0m tm1m adcr tm0tm1c ar others dat dat 0fh 01h attribute value description dbf ix fixed operand value of put, get, or movt instruction fixed operand value of inc instruction symbolic name C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC C CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCC CCCCCCCCCCCCCCC appendix a development of m pd171 subseries 261 a/d timer serial interface : 4ch : 3ch : 1ch pd17137a pd17136a pd17135a pd17134a rom: 4 kb, ceramic rom: 4kb, rc rom: 2 kb, ceramic rom: 2 kb, rc pd17149 pd17147 pd17145 rom: 8 kb, ceramic rom: 4 kb, ceramic rom: 2 kb, ceramic a/d timer serial interface : 4ch : 3ch : 1ch comparator timer serial interface : 4ch : 1ch : 1ch timer serial interface : 1ch : 1ch pd17133 pd17132 rom: 2 kb, ceramic rom: 2 kb, rc pd17121 pd17120 rom: 1.5 kb, ceramic rom: 1.5 kb, rc pd17104l pd17104 pd17108l pd17108 ceramic, low-voltage: 1.8 v min. ceramic rc: low-voltage: 1.5 v min. rc rom 1 kb rom 1 kb pd17103l pd17103 pd17107l pd17107 ceramic, low-voltage: 1.8 v min. ceramic rc, low-voltage: 1.5 v min. rc tiny controller small general-purpose controllers (one-time prom model is available for all models.) number of pins 16 22 24 28 performance medium-voltage port ac zerocross 262 [memo] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 263 appendix b comparison of functions between m pd17135a, 17137a, and m pd17145 subseries (1/2) m pd17145 m pd17147 m pd17149 m pd17135a m pd17137a rom 2k bytes 4k bytes 8k bytes 2k bytes 4k bytes ram 110 4 bits 112 4 bits stack address stack 5 levels interrupt stack 3 levels instruction execution time 2 m s (f x = 8 mhz, v dd = 4.5 to 5.5 v) 2 m s (f x = 8 mhz, v dd = 4.5 to 5.5 v) (clock, supply voltage) 4 m s (f x = 4 mhz, v dd = 3.6 to 5.5 v) 4 m s (f x = 4 mhz, v dd = 2.7 to 5.5 v) 8 m s (f x = 2 mhz, v dd = 2.7 to 5.5 v) i/o cmos i/o 12 (p0a, p0b, p0c) input 2 (p0f 0 , p0f 1 ) 1 (p1b 0 ) sense input 1 (int) 1 (int) can be pulled up by mask option n-ch open-drain i/o 8 (p0d, p0e, voltage: v dd ) 8 (p0d, p1a, voltage: 9 v) p0d pull up: software p0d pull up: mask option p0e pull up: software p1a pull up: mask option internal pull-up resistor 100 k w typ. (except p0d) 100 k w typ. 10 k w typ. (p0d) a/d converter (supply voltage) 8 bits 4 channels (v dd = 4.0 to 5.5 v) 8 bits 4 channels (v dd = 4.5 to 5.5 v) reference voltage pin v ref (v ref = 2.5 to v dd ) none (v ref = v adc = v dd ) timer 8 bits (tm0, tm1) 2 (timer output: tm1out) 2 (timer output: tm0out) tm0 clock : f x /512 tm0 clock : f x /256 f x /64 f x /64 f x /16 f x /16 int int tm1 clock : f x /8192 tm1 clock : f x /1024 f x /128 f x /512 f x /16 f x /256 tm0 count up tm0 count up basic interval timer 1 (multiplexed with watchdog timer) 1 (multiplexed with watchdog timer) (btm) count pulse : f x /16384 count pulse : f x /8192 f x /4096 f x /4096 f x /512 tm0 count up f x /16 int interrupt external 1 1 (with ac zero cross detection function) internal 4 (tm0, tm1, btm, sio) sio 1 (clocked 3-wire) output latch independent of p0d 1 latch multiplexed with p0d 1 latch 264 (2/2) m pd17145 m pd17147 m pd17149 m pd17135a m pd17137a standby function halt, stop halt, stop (with input pin rls for releasing) oscillation stabilization wait time 128 256 counts 512 256 counts poc function mask option internal package 28-pin plastic sdip (400 mil) 28-pin plastic sop (375 mil) one-time prom m pd17p149 m pd17p137a caution the m pd17145 subseries is not pin-compatible with the m pd17135a and 17137a. the m pd17145 subseries has no model equivalent to the m pd17134a and 17136a (rc oscillation type). for the electrical characteristics, refer to the data sheet of each model. remark f x : system clock oscillation frequency appendix b comparison of functions between m pd17135a, 17137a, and m pd17145 subseries 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 265 appendix c development tools the following support tools are available for developing programs for the m pd17134a subseries. hardware name in-circuit emulator ie-17k ie-17k-et note1 emu-17k note2 prom programmer af-9703 note4 af-9704 note4 af-9705 note4 af-9706 note4 se board (se-17134) emulation probe (ep-17k28ct) emulation probe (ep-17k28gt) conversion adapter (ev-9500gt-28 note3 ) outline these are in-circuit emulators that can be commonly used with microcontrollers in 17k series. ie-17k and ie-17k-et are connected to a host machine, nec pc-9800 series or ibm pc/at tm , through rs-232-c. emu-17k is mounted in expansion slot of nec pc-9800 series that serves as host machine. when these in-circuit emulators are used in combination with the evaluation board (se board) dedicated to each model of microcontroller, they operate as emulators corresponding to microcontroller. when these in-circuit emulators are used with man-machine interface software simplehost tm , a more sophisticated debugging environment can be created. emu-17k also has a function that allows you to monitor data memory contents real-time. se-17134 is an se board for m pd17134a subseries series. it can be used alone for system evaluation or in combination with an in-circuit emulator for debugging. ep-17k28ct is an emulation probe for 17k series 28-pin shrink dip (400 mil) and connects se board and target system. ep-17k28gt is an emulation probe for 17k series 28-pin sop (375 mil) and connects se board and target system by being used with ev-9500gt-28 note3 . ev-9500gt-28 is an adapter for 28-pin sop (375 mil) and is used to connect ep-17k28gt to target system. af-9703, af-9704, af-9705, and af-9706 are prom programmers corresponding to m pd17p136a and 17p137a. when connected with program adapter af-9808f, these programmers can be used to program m pd17p136a and 17p137a. af-9808f is an adapter for programming m pd17p136a and 17p137a, and is used in combination with af-9703, af-9704 or af-9706. programmer adapter (af-9808f note4 ) notes 1. low-price model: external power supply type 2. this is a program of ic corp. for details, consult ic. 3. two ev-9500gt-28 are supplied as accessories with the ep-17k28gt. five ev-9500gt-28's are optionally available as a set. 4. manufactured by ando electric. for details, consult ando electric. 266 name description distribution media host machine part number 17k series assembler (as17k) device file (as17134) support software ( simplehost ) software os as17k is an assembler applicable to the 17k series. in developing m pd17134a, 17135a, 17136a, and 17137a programs, as17k is used in combination with a device file (as17134). as17134 is a device file for the m pd17134a, 17135a, 17136a, and 17137a. it is used together with the assembler (as17k) which is applicable to the 17k series. simplehost , running on the windows tm , provides man- machine-interface in develop- ing programs by using a personal computer and the in- circuit emulator. remark the supported os versions are as follows: os version ms-dos ver. 3.30 to ver. 5.00a note pc dos ver. 3.1 to ver. 5.0 note windows ver. 3.0 to ver. 3.1 note although ms-dos ver. 5.00/5.00a and pc dos ver. 5.0 have a task swap function, this function cannot be used with this software. 5-inch, 2hd 3.5-inch, 2hd 5-inch, 2hc 5-inch, 2hd 3.5-inch, 2hd 5-inch, 2hc 5-inch, 2hd 3.5-inch, 2hd 5-inch, 2hc m s5a10as17k m s5a13as17k m s7b10as17k m s5a10as17134 m s5a13as17134 m s7b10as17134 m s5a10ie17k m s5a13ie17k m s7b10ie17k windows pc dos ms-dos pc dos ms-dos pc dos tm ms-dos tm pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at appendix c development tools 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 267 appendix d notes on configuration of system clock oscillation circuit the system clock oscillation circuit oscillates by using a ceramic resonator connected across the x1 and x2 pins or an oscillation resistor connected across the osc 1 and osc 0 pins. figure d-2 shows the external circuits of the system clock oscillation circuit. figure d-1. external circuit of system clock oscillation circuit caution wire the system clock oscillation circuit so that the resistance component and inductance component of the ground wiring can be minimized. wire the portion enclosed in the dotted line in figure d-1 as follows to prevent influence of wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. keep a distance between the wiring and a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . do not ground the wiring to a ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. figure d-2 shows an examples of incorrect oscillation circuits. ceramic resonator x out x in gnd pd17135a pd17137a pd17p137a pd17134a pd17136a pd17p136a osc 0 osc 1 oscillation resistor m m m m m m 268 figure d-2. example of incorrect oscillation circuits (a) wiring length of circuit is too long. (b) crossed signal lines (c) signal line close to high alternating current (d) current flowing through ground line of oscillation circuit (potential at points a and b changes in respect to point c) (e) signal is extracted appendix d notes on configuration of system clock oscillation circuit too long x out x in gnd x out x in gnd port x out x in gnd high current x out x in gnd port high current ab c x out x in gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 269 appendix e instruction list e.1 instruction list (by function) [addition instructions] add r, m ... 198 add m, #n4 ... 201 addc r, m ... 203 addc m, #n4 ... 205 inc ar ... 206 inc ix ... 208 [subtraction instructions] sub r, m ... 209 sub m, #n4 ... 211 subc r, m ... 212 subc m, #n4 ... 214 [logical operation instructions] or r, m ... 216 or m, #n4 ... 216 and r, m ... 217 and m, #n4 ... 218 xor r, m ... 219 xor m, #n4 ... 220 [judgment instructions] skt m, #n ... 221 skf m, #n ... 223 [comparison instructions] ske m, #n4 ... 223 skne m, #n4 ... 223 skge m, #n4 ... 224 sklt m, #n4 ... 224 [rotation instructions] rorc r ... 226 [transfer instructions] ld r, m ... 227 st m, r ... 228 mov @r, m ... 231 mov m, @r ... 231 mov m, #n4 ... 233 movt dbf, @ar ... 234 push ar ... 235 pop ar ... 237 peek wr, rf ... 238 poke rf, wr ... 239 get dbf, p ... 240 put p, dbf ... 241 [branch instructions] br addr ... 243 br @ar ... 243 [subroutine instructions] call addr ... 246 call @ar ... 247 ret ... 249 retsk ... 249 reti ... 250 [interrupt instructions] ei ... 251 di ... 252 [other instructions] stop s ... 253 halt h ... 253 nop ... 253 270 e.2 iinstruction list (alphabetical order) [a] add m, #n4 ... 201 add r, m ... 198 addc m, #n4 ... 205 addc r, m ... 203 and m, #n4 ... 218 and r, m ... 217 [b] br addr ... 243 br @ar ... 243 [c] call addr ... 246 call @ar ... 247 [d] di ... 252 [e] ei ... 251 [g] get dbf, p ... 240 [h] halt h ... 253 [i] inc ar ... 206 inc ix ... 208 [l] ld r, m ... 227 [m] mov m, #n4 ... 233 mov m, @r ... 231 mov @r, m ... 231 movt dbf, @ar ... 234 [n] nop ... 253 [o] or m, #n4 ... 216 or r, m ... 216 [p] peek wr, rf ... 238 poke rf, wr ... 239 pop ar ... 237 push ar ... 235 put p, dbf ... 241 [r] ret ... 249 reti ... 250 retsk ... 249 rorc r ... 226 [s] ske m, #n4 ... 223 skf m, #n ... 221 skge m, #n4 ... 224 sklt m, #n4 ... 224 skne m, #n4 ... 223 skt m, #n ... 221 st m, r ... 228 stop s ... 253 sub m, #n4 ... 211 sub r, m ... 209 subc m, #n4 ... 214 subc r, m ... 212 [x] xor m, #n4 ... 220 xor r, m ... 219 appendix e instruction list 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 271 appendix f ordering mask rom after developing the program, place an order for the mask rom version, according to the following procedure: (1) make reservation when ordering mask rom. advise nec of the schedule for placing an order for the mask rom. if nec is not informed in advance, on- time delivery may not be possible. (2) create ordering medium. use uv-eprom to place an order for the mask rom. add /prom as an assemble option of the assembler (as17k), and create a mask rom ordering hex file (with extender for .pro). next, write the mask rom ordering hex file into the uv-eprom. create three uv-eproms with the same contents. (3) prepare necessary documents. fill out the following forms to place an order for the mask rom: ? mask rom ordering sheet ? mask rom ordering check sheet (4) ordering submit the media created in (2) and documents prepared in (3) to nec by the specified date. caution for details, refer to information document rom code ordering procedure (iem-1366). 272 [memo] although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-889-1689 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec corporation semiconductor solution engineering division technical information support dept. fax: 044-548-7900 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 96.8 name company from: tel. fax facsimile message |
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